LTC4269-1
23
42691fc
Enable Delay Time (ENDLY)
The fl yback pulse appears when the primary-side switch
shuts off. However, it takes a fi nite time until the transformer
primary-side voltage waveform represents the output
voltage. This is partly due to rise time on the primary-
side MOSFET drain node, but, more importantly, is due
to transformer leakage inductance. The latter causes a
voltage spike on the primary side, not directly related to
output voltage. Some time is also required for internal
settling of the feedback amplifi er circuitry. In order to
maintain immunity to these phenomena, a fi xed delay is
introduced between the switch turn-off command and the
enabling of the feedback amplifi er. This is termed “enable
delay.” In certain cases where the leakage spike is not
suffi ciently settled by the end of the enable delay period,
regulation error may result. See the subsequent sections
for further details.
Collapse Detect
Once the feedback amplifi er is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, which compares the fl yback
voltage (FB) to a fi xed reference, nominally 80% of V
FB
.
When the fl yback waveform drops below this level, the
feedback amplifi er is disabled.
Minimum Enable Time
The feedback amplifi er, once enabled, stays on for a fi xed
minimum time period, termed “minimum enable time.”
This prevents lockup, especially when the output voltage
is abnormally low, e.g., during start-up. The minimum
enable time period ensures that the V
CMP
node is able to
“pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. This time is set internally.
Effects of Variable Enable Period
The feedback amplifi er is enabled during only a portion of
the cycle time. This can vary from the fi xed minimum enable
time described to a maximum of roughly the off switch
time minus the enable delay time. Certain parameters of
feedback amp behavior are directly affected by the variable
enable period. These include effective transconductance
and V
CMP
node slew rate.
Load Compensation Theory
The LTC4269-1 uses the flyback pulse to obtain
information about the isolated output voltage. An error
source is caused by transformer secondary current fl ow
through the synchronous MOSFET R
DS(ON)
and real life
nonzero impedances of the transformer secondary and
output capacitor. This was represented previously by the
expression, I
SEC
• (ESR + R
DS(ON)
). However, it is generally
more useful to convert this expression to effective output
impedance. Because the secondary current only fl ows
during the off portion of the duty cycle (DC), the effective
output impedance equals the lumped secondary impedance
divided by off time DC.
Since the off-time duty cycle is equal to 1 – DC, then:
R
S(OUT)
=
ESR+R
DS(ON)
1−DC
where:
R
S(OUT)
= effective supply output impedance
DC = duty cycle
R
DS(ON)
and ESR are as defi ned previously
This impedance error may be judged acceptable in less
critical applications, or if the output load current remains
relatively constant. In these cases, the external FB resistive
divider is adjusted to compensate for nominal expected
error. In more demanding applications, output impedance
error is minimized by the use of the load compensation
function. Figure 11 shows the block diagram of the load
compensation function. Switch current is converted to a
voltage by the external sense resistor, averaged and lowpass
fi ltered by the internal 50k resistor R
CMPF
and the external
capacitor on C
CMP
. This voltage is impressed across the
external R
CMP
resistor by op amp A1 and transistor Q3
producing a current at the collector of Q3 that is subtracted
from the FB node. This effectively increases the voltage
required at the top of the R1/R2 feedback divider to achieve
equilibrium.
The average primary-side switch current increases to
maintain output voltage regulation as output loading
increases. The increase in average current increases R
CMP
resistor current which affects a corresponding increase
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