LTC4269-1
25
42691fc
Note the use of the external feedback resistive divider
ratio to set output voltage provides the user additional
freedom in selecting a suitable transformer turns ratio.
Turns ratios that are the simple ratios of small integers;
e.g., 1:1, 2:1, 3:2 help facilitate transformer construction
and improve performance.
When building a supply with multiple outputs derived
through a multiple winding transformer, lower duty cycle
can improve cross regulation by keeping the synchronous
rectifi er on longer, and thus, keep secondary windings
coupled longer. For a multiple output transformer, the turns
ratio between output windings is critical and affects the
accuracy of the voltages. The ratio between two output
voltages is set with the formula V
OUT2
= V
OUT1
• N21 where
N21 is the turns ratio between the two windings. Also
keep the secondary MOSFET R
DS(ON)
small to improve
cross regulation.
The feedback winding usually provides both the feedback
voltage and power for the LTC4269-1. Set the turns ratio
between the output and feedback winding to provide a
rectifi ed voltage that under worst-case conditions is greater
than the 11V maximum V
CC
turn-off voltage.
N
SF
>
V
OUT
11+ V
F
where:
V
F
=Diode Forward Voltage
For our example: N
SF
>
5
11+0.7
=
1
2.34
We will choose
1
3
Leakage Inductance
Transformer leakage inductance (on either the primary or
secondary) causes a spike after the primary-side switch
turn-off. This is increasingly prominent at higher load
currents, where more stored energy is dissipated. Higher
yback voltage may break down the MOSFET switch if it
has too low a BV
DSS
rating.
One solution to reducing this spike is to use a clamp circuit
to suppress the voltage excursion. However, suppressing
the voltage extends the fl yback pulse width. If the fl yback
pulse extends beyond the enable delay time, output
voltage regulation is affected. The feedback system has a
deliberately limited input range, roughly ±50mV referred
to the FB node. This rejects higher voltage leakage spikes
because once a leakage spike is several volts in amplitude,
a further increase in amplitude has little effect on the
feedback system. Therefore, it is advisable to arrange the
clamp circuit to clamp at as high a voltage as possible,
observing MOSFET breakdown, such that leakage spike
duration is as short as possible. Application Note 19
provides a good reference on clamp design.
As a rough guide, leakage inductance of several percent
(of mutual inductance) or less may require a clamp, but
exhibit little to no regulation error due to leakage spike
behavior. Inductances from several percent up to, perhaps,
ten percent, cause increasing regulation error.
Avoid double digit percentage leakage inductances. There
is a potential for abrupt loss of control at high load current.
This curious condition potentially occurs when the leakage
spike becomes such a large portion of the fl yback waveform
that the processing circuitry is fooled into thinking that the
leakage spike itself is the real fl yback signal!
It then reverts to a potentially stable state whereby the
top of the leakage spike is the control point, and the
trailing edge of the leakage spike triggers the collapse
detect circuitry. This typically reduces the output voltage
abruptly to a fraction, roughly one-third to two-thirds of
its correct value.
Once load current is reduced suffi ciently, the system snaps
back to normal operation. When using transformers with
considerable leakage inductance, exercise this worst-case
check for potential bistability:
1. Operate the prototype supply at maximum expected
load current.
2. Temporarily short-circuit the output.
3. Observe that normal operation is restored.
If the output voltage is found to hang up at an abnormally
low value, the system has a problem. This is usually evident
by simultaneously viewing the primary-side MOSFET drain
voltage to observe fi rsthand the leakage spike behavior.
APPLICATIONS INFORMATION
LTC4269-1
26
42691fc
APPLICATIONS INFORMATION
A fi nal note—the susceptibility of the system to bistable
behavior is somewhat a function of the load current/
voltage characteristics. A load with resistive—i.e., I = V/R
behavior—is the most apt to be bistable. Capacitive loads
that exhibit I = V
2
/R behavior are less susceptible.
Secondary Leakage Inductance
Leakage inductance on the secondary forms an inductive
divider on the transformer secondary, reducing the size
of the fl yback pulse. This increases the output voltage
target by a similar percentage. Note that unlike leakage
spike behavior, this phenomenon is independent of load.
Since the secondary leakage inductance is a constant
percentage of mutual inductance (within manufacturing
variations), the solution is to adjust the feedback resistive
divider ratio to compensate.
Winding Resistance Effects
Primary or secondary winding resistance acts to reduce
overall effi ciency (P
OUT
/P
IN
). Secondary winding resistance
increases effective output impedance, degrading load regu-
lation. Load compensation can mitigate this to some extent
but a good design keeps parasitic resistances low.
Bifi lar Winding
A bifi lar, or similar winding, is a good way to minimize
troublesome leakage inductances. Bifi lar windings also
improve coupling coeffi cients, and thus improve cross
regulation in multiple winding transformers. However,
tight coupling usually increases primary-to-secondary
capacitance and limits the primary-to-secondary
breakdown voltage, so is not always practical.
Primary Inductance
The transformer primary inductance, L
P
, is selected
based on the peak-to-peak ripple current ratio (X) in the
transformer relative to its maximum value. As a general
rule, keep X in the range of 20% to 40% (i.e., X = 0.2 to
0.4). Higher values of ripple will increase conduction losses,
while lower values will require larger cores.
Ripple current and percentage ripple is largest at minimum
duty cycle; in other words, at the highest input voltage.
L
P
is calculated from the following equation.
L
P
=
V
IN(MAX)
•DC
MIN
()
2
f
OSC
•X
MAX
•P
IN
=
V
IN(MAX)
•DC
MIN
()
2
•Eff
f
OSC
•X
MAX
•P
OUT
where:
f
OSC
is the oscillator frequency
DC
MIN
is the DC at maximum input voltage
X
MAX
is ripple current ratio at maximum input voltage
Using common high power PoE values, a 48V (41V < V
IN
< 57V) to 5V/5.3A converter with 90% effi ciency, P
OUT
=
26.5W and P
IN
= 29.5W. Using X = 0.4 N = 1/8 and f
OSC
= 200kHz:
DC
MIN
=
1
1+
N•V
IN(MAX)
V
OUT
=
1
1+
1
8
57
5
= 41.2%
L
P
=
57V 0.412
()
2
200kHz 0.4 26.5W
= 260µH
Optimization might show that a more effi cient solution
is obtained at higher peak current but lower inductance
and the associated winding series resistance. A simple
spreadsheet program is useful for looking at trade-offs.
Transformer Core Selection
Once L
P
is known, the type of transformer is selected. High
effi ciency converters use ferrite cores to minimize core
loss. Actual core loss is independent of core size for a fi xed
inductance, but decreases as inductance increases. Since
increased inductance is accomplished through more turns
of wire, copper losses increase. Thus, transformer design
balances core and copper losses. Remember that increased
winding resistance will degrade cross regulation and
increase the amount of load compensation required.
The main design goals for core selection are reducing
copper losses and preventing saturation. Ferrite core
material saturates hard, rapidly reducing inductance
when the peak design current is exceeded. This results
LTC4269-1
27
42691fc
APPLICATIONS INFORMATION
in an abrupt increase in inductor ripple current and,
consequently, output voltage ripple. Do not allow the core
to saturate! The maximum peak primary current occurs
at minimum V
IN
:
I
PK
=
P
IN
V
IN(MIN)
•DC
MAX
•1+
X
MIN
2
now :
DC
MAX
=
1
1+
N•V
IN MIN
()
V
OUT
=
1
1+
1
8
41
5
= 49.4%
X
MIN
=
V
IN(MIN)
•DC
MAX
()
2
f
OSC
•L
P
•P
IN
=
41• 49.4%
()
2
200kHz 260µH 29.5W
= 0.267
Using the example numbers leads to:
I
PK
=
29.5W
41• 0.494
•1+
0.267
2
= 1.65A
Multiple Outputs
One advantage that the fl yback topology offers is that
additional output voltages can be obtained simply by adding
windings. Designing a transformer for such a situation is
beyond the scope of this document. For multiple windings,
realize that the fl yback winding signal is a combination of
activity on all the secondary windings. Thus load regulation
is affected by each winding’s load. Take care to minimize
cross regulation effects.
Setting Feedback Resistive Divider
The expression for V
OUT
developed in the Operation section
is rearranged to yield the following expression for the
feedback resistors:
R1=R2
V
OUT
+I
SEC
•ESR+R
DS(ON)
()
V
FB
•N
SF
1
Continuing the example, if ESR + R
DS(ON)
= 8mΩ, R2 =
3.32k, then:
R1= 3.32k
5+5.3 0.008
1.237 1/ 3
1
= 37.28k
choose 37.4k.
It is recommended that the Thevenin impedance of the
resistive divider (R1||R2) is roughly 3k for bias current
cancellation and other reasons.
Current Sense Resistor Considerations
The external current sense resistor is used to control peak
primary switch current, which controls a number of key
converter characteristics including maximum power and
external component ratings. Use a noninductive current
sense resistor (no wire-wound resistors). Mounting the
resistor directly above an unbroken ground plane connected
with wide and short traces keeps stray resistance and
inductance low.
The dual sense pins allow for a full Kelvin connection. Make
sure that SENSE+ and SENSE– are isolated and connect
close to the sense resistor.
Peak current occurs at 100mV of sense voltage V
SENSE
. So
the nominal sense resistor is V
SENSE
/I
PK
. For example, a
peak switch current of 10A requires a nominal sense resistor
of 0.010Ω Note that the instantaneous peak power in the
sense resistor is 1W, and that it is rated accordingly. The
use of parallel resistors can help achieve low resistance,
low parasitic inductance and increased power capability.
Size R
SENSE
using worst-case conditions, minimum L
P
,
V
SENSE
and maximum V
IN
. Continuing the example, let us
assume that our worst-case conditions yield an I
PK
of 40%
above nominal, so I
PK
= 2.3A. If there is a 10% tolerance
on R
SENSE
and minimum V
SENSE
= 88mV, then R
SENSE
110% = 88mV/2.3A and nominal R
SENSE
= 35mΩ. Round
to the nearest available lower value, 33mΩ.

LTC4269CDKD-1#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN IEEE 802.3at High Power PD Controller with Flyback Switcher
Lifecycle:
New from this manufacturer.
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