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LTC4269CDKD-1#PBF

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LTC4269-1
34
42691fc
APPLICATIONS INFORMATION
For each secondary-side power MOSFET, the BV
DSS
should
be greater than:
BV
DSS
≥ V
OUT
+ V
IN(MAX)
• N
SP
Choose the primary-side MOSFET R
DS(ON)
at the nominal
gate drive voltage (7.5V). The secondary-side MOSFET gate
drive voltage depends on the gate drive method.
Primary-side power MOSFET RMS current is given by:
I
RMS(PRI)
=
P
IN
V
IN(MIN)
DC
MAX
For each secondary-side power MOSFET RMS current is
given by:
I
RMS(SEC)
=
I
OUT
1−DC
MAX
Calculate MOSFET power dissipation next. Because the
primary-side power MOSFET operates at high V
DS
, a
transition power loss term is included for accuracy. C
MILLER
is the most critical parameter in determining the transition
loss, but is not directly specifi ed on the data sheets.
C
MILLER
is calculated from the gate charge curve included
on most MOSFET data sheets (Figure 16).
With C
MILLER
determined, calculate the primary-side power
MOSFET power dissipation:
P
D(PRI)
=I
RMS(PRI)
2
•R
DS(ON)
1+δ
()
+
V
IN(MAX)
•
P
IN(MAX)
DC
MIN
•R
DR
•
C
MILLER
V
GATE(MAX)
− V
TH
•f
OSC
where:
R
DR
is the gate driver resistance (≈10Ω)
V
TH
is the MOSFET gate threshold voltage
f
OSC
is the operating frequency
V
GATE(MAX)
= 7.5V for this part
(1 + δ) is generally given for a MOSFET in the form of a
normalized R
DS(ON)
vs temperature curve. If you don’t have
a curve, use δ = 0.005/°C • ΔT for low voltage MOSFETs.
The secondary-side power MOSFETs typically operate
at substantially lower V
DS
, so you can neglect transition
losses. The dissipation is calculated using:
P
DIS(SEC)
= I
RMS(SEC)
2
• R
DS(ON)
(1 + δ)
With power dissipation known, the MOSFETs’ junction
temperatures are obtained from the equation:
T
J
= T
A
+ P
DIS
• θ
JA
where T
A
is the ambient temperature and θ
JA
is the MOSFET
junction to ambient thermal resistance.
Once you have T
J
iterate your calculations recomputing
δ and power dissipations until convergence.
Gate Drive Node Consideration
The PG and SG gate drivers are strong drives to minimize
gate drive rise and fall times. This improves effi ciency,
but the high frequency components of these signals can
cause problems. Keep the traces short and wide to reduce
parasitic inductance.
The parasitic inductance creates an LC tank with the
MOSFET gate capacitance. In less than ideal layouts, a
series resistance of 5Ω or more may help to dampen the
ringing at the expense of slightly slower rise and fall times
and poorer effi ciency.
The LTC4269-1 gate drives will clamp the max gate voltage
Q
A
V
GS
ab
42691 F16
Q
B
MILLER EFFECT
GATE CHARGE (Q
G
)
Figure 16. Gate Charge Curve
The fl at portion of the curve is the result of the Miller (gate
to-drain) capacitance as the drain voltage drops. The Miller
capacitance is computed as:
C
MILLER
=
Q
B
−Q
A
V
DS
The curve is done for a given V
DS
. The Miller capacitance
for different V
DS
voltages are estimated by multiplying the
computed C
MILLER
by the ratio of the application V
DS
to
the curve specifi ed V
DS
.
LTC4269-1
35
42691fc
APPLICATIONS INFORMATION
to roughly 7.5V, so you can safely use MOSFETs with
maximum V
GS
of 10V and larger.
Synchronous Gate Drive
There are several different ways to drive the synchronous
gate MOSFET. Full converter isolation requires the synchro-
nous gate drive to be isolated. This is usually accomplished
by way of a pulse transformer. Usually the pulse driver is
used to drive a buffer on the secondary, as shown in the
application on the front page of this data sheet.
However, other schemes are possible. There are gate drivers
and secondary-side synchronous controllers available that
provide the buffer function as well as additional features.
Capacitor Selection
In a fl yback converter, the input and output current fl ows
in pulses, placing severe demands on the input and output
fi lter capacitors. The input and output fi lter capacitors are
selected based on RMS current ratings and ripple voltage.
Select an input capacitor with a ripple current rating
greater than:
I
RMS(PRI)
=
P
IN
V
IN(MIN)
1−DC
MAX
DC
MAX
Continuing the example:
I
RMS(PRI)
=
29.5W
41V
1−49.4%
49.4%
= 0.728A
Keep input capacitor series resistance (ESR) and inductance
(ESL) small, as they affect electromagnetic interference
suppression. In some instances, high ESR can also
produce stability problems because fl yback converters
exhibit a negative input resistance characteristic. Refer
to Application Note 19 for more information.
The output capacitor is sized to handle the ripple current
and to ensure acceptable output voltage ripple. The output
capacitor should have an RMS current rating greater
than:
I
RMS(SEC)
=I
OUT
DC
MAX
1−DC
MAX
Continuing the example:
I
RMS(SEC)
= 5.3A
49.4%
1−49.4%
= 5.24A
This is calculated for each output in a multiple winding
application.
ESR and ESL along with bulk capacitance directly affect the
output voltage ripple. The waveforms for a typical fl yback
converter are illustrated in Figure 17.
The maximum acceptable ripple voltage (expressed as a
percentage of the output voltage) is used to establish a
starting point for the capacitor values. For the purpose of
simplicity, we will choose 2% for the maximum output
OUTPUT VOLTAGE
RIPPLE WAVEFORM
SECONDARY
CURRENT
PRIMARY
CURRENT
I
PRI
∆V
COUT
42691 F17
RINGING
DUE TO ESL
I
PRI
N
∆V
ESR
Figure 17. Typical Flyback Converter Waveforms
ripple, divided equally between the ESR step and the
charging/discharging ΔV. This percentage ripple changes,
depending on the requirements of the application. You can
modify the following equations.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor is determined by:
ESR
COUT
≤ 1% •
V
OUT
•1−DC
MAX
()
I
OUT
LTC4269-1
36
42691fc
The other 1% is due to the bulk C component, so use:
C
OUT
≥
I
OUT
1% • V
OUT
•f
OSC
In many applications, the output capacitor is created from
multiple capacitors to achieve desired voltage ripple,
reliability and cost goals. For example, a low ESR ceramic
capacitor can minimize the ESR step, while an electrolytic
capacitor satisfi es the required bulk C.
Continuing our example, the output capacitor needs:
ESR
COUT
≤ 1% •
5V • 1−49.4%
()
5.3A
= 4mΩ
C
OUT
≥
5.3A
1%•5•200kHz
= 600µF
These electrical characteristics require paralleling several
low ESR capacitors possibly of mixed type.
One way to reduce cost and improve output ripple is to use a
simple LC fi lter. Figure 18 shows an example of the fi lter.
APPLICATIONS INFORMATION
optimization of output ripple must be done on a dedicated
PC board. Parasitic inductance due to poor layout can
signifi cantly impact ripple. Refer to the PC Board Layout
section for more details.
ELECTRO STATIC DISCHARGE AND SURGE
PROTECTION
The LTC4269-1 is specifi ed to operate with an absolute
maximum voltage of –100V and is designed to tolerate
brief overvoltage events. However, the pins that interface
to the outside world (primarily V
PORTN
and V
PORTP
)
can routinely see peak voltages in excess of 10kV. To
protect the LTC4269-1, it is highly recommended that the
SMAJ58A unidirectional 58V transient voltage suppressor
be installed between the diode bridge and the LTC4269-1
(D3 in Figure 2).
ISOLATION
The 802.3 standard requires Ethernet ports to be electrically
isolated from all other conductors that are user accessible.
This includes the metal chassis, other connectors and
any auxiliary power connection. For PDs, there are two
common methods to meet the isolation requirement. If
there will be any user accessible connection to the PD,
then an isolated DC/DC converter is necessary to meet
the isolation requirements. If user connections can be
avoided, then it is possible to meet the safety requirement
by completely enclosing the PD in an insulated housing.
In all PD applications, there should be no user accessible
electrical connections to the LTC4269-1 or support circuitry
other than the RJ-45 port.
LAYOUT CONSIDERATIONS FOR THE LTC4269-1
The LTC4269-1’s PD front end is relatively immune to
layout problems. Excessive parasitic capacitance on the
R
CLASS
pin should be avoided. Include a PCB heat sink
to which the exposed pad on the bottom of the package
can be soldered. This heat sink should be electrically
connected to GND. For optimum thermal performance,
make the heat sink as large as possible. Voltages in a
PD can be as large as 57V for PoE applications, so high
voltage layout techniques should be employed. The SHDN
R
LOAD
C
OUT2
1µF
V
OUT
C
OUT
470µF
C1
47µF
s3
FROM
SECONDARY
WINDING
L1, 0.1µH
42691 F18
++
Figure 18.
The design of the fi lter is beyond the scope of this data
sheet. However, as a starting point, use these general
guidelines. Start with a C
OUT
1/4 the size of the nonfi lter
solution. Make C1 1/4 of C
OUT
to make the second fi lter
pole independent of C
OUT
. C1 may be best implemented
with multiple ceramic capacitors. Make L1 smaller than
the output inductance of the transformer. In general, a
0.1µH fi lter inductor is suffi cient. Add a small ceramic
capacitor (C
OUT2
) for high frequency noise on V
OUT
. For
those interested in more details refer to “Second-Stage
LC Filter Design,” Ridley, Switching Power Magazine, July
2000 p8-10.
Circuit simulation is a way to optimize output capacitance
and fi lters, just make sure to include the component
parasitic. LTC SwitcherCAD
TM
is a terrifi c free circuit
simulation tool that is available at www.linear.com. Final
SwitcherCAD is a trademark of Linear Technology Corporation.
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LTC4269CDKD-1#PBF

Mfr. #:
Buy LTC4269CDKD-1#PBF
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN IEEE 802.3at High Power PD Controller with Flyback Switcher
Lifecycle:
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