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MAX6876ETX+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
MAX6876
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
______________________________________________________________________________________ 19
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
5
If 1, latch-on fault
If 0, autoretry
“000” autoretry timer value = 25µs
“001” autoretry timer value = 12.5ms
“010” autoretry timer value = 25.0ms
“011” autoretry timer value = 50.0ms
“100” autoretry timer value = 100.0ms
“101” autoretry timer value = 200.0ms
“110” autoretry timer value = 400.0ms
09h 29h
[4:2]
“111” autoretry timer value = 1600.0ms
Table 5. Program Autoretry/Latch off
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT
RANGE
DESCRIPTION
00h 20h [7:0]
IN1 Undervoltage Threshold
V
TH
= 1.0 + n x 20mV (if R08[7] = 0)
V
TH
= 0.5 + n x 10mV (if R08[7] = 1)
where n is the register content decimal representation. Note that V
TH
ranges
must be 1V to 5.5V and 0.5V to 3.05V, respectively.
01h 21h [7:0]
IN2 Undervoltage Threshold
V
TH
= 1.0 + n x 20mV (if R08[6] = 0)
V
TH
= 0.5 + n x 10mV (if R08[6] = 1)
where n is the register content decimal representation. Note that V
TH
ranges
must be 1V to 5.5V and 0.5V to 3.05V, respectively.
02h 22h [7:0]
IN3 Undervoltage Threshold
V
TH
= 1.0 + n x 20mV (if R08[5] = 0)
V
TH
= 0.5 + n x 10mV (if R08[5] = 1)
where n is the register content decimal representation. Note that V
TH
ranges
must be 1V to 5.5V and 0.5V to 3.05V, respectively.
03h 23h [7:0]
IN4 Undervoltage Threshold
V
TH
= 1.0 + n x 20mV (if R08[4] = 0)
V
TH
= 0.5 + n x 10mV (if R08[4] = 1)
where n is the register content decimal representation. Note that V
TH
ranges
must be 1V to 5.5V and 0.5V to 3.05V, respectively.
04h 24h [7:0]
IN1 Overvoltage Threshold
V
TH
= 1.0 + n x 20mV (if R08[7] = 0)
V
TH
= 0.5 + n x 10mV (if R08[7] = 1)
where n is the register content decimal representation. Note that V
TH
ranges
must be 1V to 5.5V and 0.5V to 3.05V, respectively.
Table 6. IN1–IN4 Threshold Settings
MAX6876
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
20 ______________________________________________________________________________________
Manual Reset Input (
MR
)
The manual reset (MR) input initiates a reset condition.
MR is internally pulled up to ABP through a 100kΩ
resistor. When MR is low, RESET remains low for the
selected reset timeout period after MR transitions from
low to high (see the Reset Output (
RESET
) section).
Margin Input (
MARGIN
)
MARGIN allows system-level testing while power sup-
plies exceed the normal ranges. Drive MARGIN low
before varying system voltages below/above the select-
ed threshold without signaling an error. MARGIN makes
it possible to vary the supplies without a need to repro-
gram the IN_ or PG_ thresholds and prevents
tracker/sequencer alerts or faults. Drive MARGIN high
or leave it floating for normal operating mode.
ENABLE
Drive logic ENABLE input high to initiate voltage track-
ing/sequencing during power-up operation. Drive logic
ENABLE low to initiate tracking/sequencing power-down
operation. When ENABLE is not used, connect to ABP.
When the MAX6876 is configured to use the I
2
C on/off
command, a valid I
2
C signal must be received before
the device begins the power-up tracking/sequencing
routine. The internal enable logic is an AND function of
the ENABLE logic, the TRKEN logic, and the I
2
C con-
trol/command logic (Figure 7). When all three AND gate
input variables are true (and the monitored IN/OUT volt-
ages meet their required thresholds), turn-on is allowed.
When any AND input variable becomes false, the turn-
off cycle (track/sequence down) begins immediately.
Drive ENABLE and TRKEN high if only the I
2
C com-
mand is to be used to turn on/off the device. The detec-
tors monitoring IN_ and OUT_ voltages, and
overcurrent conditions have a higher priority after a
power-on routine has been initiated by the internal
enable logic. If a fault occurs during the power-up
cycle, the device is powered down immediately, inde-
pendent of ENABLE, TRKEN, and the I
2
C shutdown
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT
RANGE
DESCRIPTION
05h 25h [7:0]
IN2 Overvoltage Threshold
V
TH
= 1.0 + n x 20mV (if R08[6] = 0)
V
TH
= 0.5 + n x 10mV (if R08[6] = 1)
where n is the register content decimal representation. Note that V
TH
ranges
must be 1V to 5.5V and 0.5V to 3.05V, respectively.
06h 26h [7:0]
IN3 Overvoltage Threshold
V
TH
= 1.0 + n x 20mV (if R08[5] = 0)
V
TH
= 0.5 + n x 10mV (if R08[5] = 1)
where n is the register content decimal representation. Note that V
TH
ranges
must be 1V to 5.5V and 0.5V to 3.05V, respectively.
07h 27h [7:0]
IN4 Overvoltage Threshold
V
TH
= 1.0 + n x 20mV (if R08[4] = 0)
V
TH
= 0.5 + n x 10mV (if R08[4] = 1)
where n is the register content decimal representation. Note that V
TH
ranges
must be 1V to 5.5V and 0.5V to 3.05V, respectively.
Bit 7—If 0, 20mV steps in V
TH
setting for IN1
If 1, 10mV steps in V
TH
setting for IN1
Bit 6—If 0, 20mV steps in V
TH
setting for IN2
If 1, 10mV steps in V
TH
setting for IN2
Bit 5—If 0, 20mV steps in V
TH
setting for IN3
If 1, 10mV steps in V
TH
setting for IN3
08h 28h [7:4]
Bit 4—If 0, 20mV steps in V
TH
setting for IN4
If 1, 10mV steps in V
TH
setting for IN4
Table 6. IN1–IN4 Threshold Settings (continued)
MAX6876
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
______________________________________________________________________________________ 21
command (Table 7). If a latch-on fault mode is chosen,
a toggle on the internal enable clears the latch condi-
tion and restarts the device after a fault condition
(Figure 7).
Reference Voltage Input (REFIN)
The MAX6876 features an internal +1.25V voltage refer-
ence. The voltage reference sets the threshold of the
voltage detectors. Leave REFIN unconnected when
using the internal reference. REFIN accepts an external
reference in the +1.225V to +1.275V range. Use Table
8 commands to select the external reference.
Track Enable Input (TRKEN)
The track enable (TRKEN) monitor input is another fea-
ture of the MAX6876. To enable voltage-tracking
power-up operation, drive TRKEN higher than 1.285V.
When TRKEN goes below 1.25V, OUT_ outputs start
tracking down. Connect TRKEN to an external resistor-
divider network to set the desired monitor threshold.
Connect TRKEN to ABP if not used.
SYNCH
The MAX6876 provides selectable tracking synchro-
nization output or input (SYNCH). SYNCH allows track-
ing of up to 16 power supplies on the same I
2
C bus.
One device is programmed as the SYNCH master and
the other devices are programmed as slaves. SYNCH
of the master device outputs the common ramp voltage
to which all OUT_ voltages are tracked. The SYNCH
pins of the slave devices are inputs for the ramp control
voltage (no internal ramp is generated in the slave
devices) (see Table 1).
Monitored Outputs
OUT1–OUT4
The MAX6876 monitors four OUT_ outputs to control
the tracking/sequencing performance. After the internal
supply (ABP) exceeds the minimum voltage (2.7V)
requirements, TRKEN > 1.25V, the internal ENABLE
input is logic high, and IN1–IN4 are all within their
selected thresholds, OUT1–OUT4 will begin to track or
sequence.
During power-up mode, the MAX6876 drives the gates
of the external n-channel FETs to force the OUT_ volt-
ages to track the internally set ramp voltage. If OUT_
voltages vary from the ramp voltage by more than
±125mV, an internal comparator signals an alert that
dynamically adjusts the ramp voltage (stops the ramp
until the slow OUT_ catches up). During power-down
mode, an internal pulldown resistor (100Ω) on OUT_
can be enabled to help discharge load capacitance.
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
Bit 1—If 1, check ENABLE with I
2
C enable control bit
If 0, ignore ENABLE with I
2
C
09h 29h [1:0]
Bit 0—If 0, enable with I
2
C = 0, I
2
C enable command bit
If 1, enable with I
2
C = 1
Table 7. Program ENABLE
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
11h 31h 0 Bit 0—If 1, selects external reference; 0 selects internal reference
Table 8. Select External Reference
ENABLE
INTERNAL
ENABLE
TRKEN
I
2
C ENABLE CONTROL BIT
(RAM REGISTER)
1 = YES
0 = NO
I
2
C ENABLE COMMAND BIT
(RAM REGISTER)
0 = OFF
1 = ON
09h[0]
09h[1]
V
TRKEN
Figure 7. Logic ENABLE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39

MAX6876ETX+T

Mfr. #:
Buy MAX6876ETX+T
Manufacturer:
Maxim Integrated
Description:
Supervisory Circuits EEPROM-Prog Quad Power-Sup Sequence
Lifecycle:
New from this manufacturer.
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