MAX6876
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
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6) The master generates a repeated start condition.
7) The master sends the 7-bit slave address and a
read bit (high).
8) The slave asserts an ACK on SDA.
9) The slave sends the 8-bit byte count (16).
10) The master asserts an ACK on SDA.
11) The slave sends 8 bits of data.
12) The master asserts an ACK on SDA.
13) Repeat steps 8 and 9 fifteen times.
14) The master generates a stop condition.
Address Pointers
Use the send byte protocol to set the register address
pointers before read and write operations. For the con-
figuration registers, valid address pointers range from
00h to 13h. Register addresses outside of this range
result in a NACK being issued from the MAX6876.
When using the block write protocol, the address point-
er automatically increments after each data byte,
except when the address pointer is already at 13h. If
the address pointer is already 13h, and more data
bytes are being sent, these subsequent bytes overwrite
address 13h repeatedly, leaving only the last data byte
sent stored at this register address.
For the configuration EEPROM, valid address pointers
range from 20h to 33h. When using the block write pro-
tocol, the address pointer automatically increments
after each data byte, except when the address pointer
is already at 33h. If the address pointer is already 33h,
and more data bytes are being sent, these subsequent
bytes overwrite address 33h repeatedly, leaving only
the last data byte sent stored at this register address.
Configuration EEPROM
The configuration EEPROM addresses range from 20h
to 33h. Write data to the configuration EEPROM to auto-
matically set up the MAX6876 upon power-up. Data
transfers from the configuration EEPROM to the config-
uration registers when ABP exceeds UVLO during
power-up. After ABP exceeds UVLO, an internal 1MHz
clock starts after a 5µs delay, and data transfer begins.
Data transfer disables access to the configuration reg-
isters and EEPROM. The data transfer from EEPROM to
the configuration registers takes 2ms (max). Read con-
figuration EEPROM data at any time after power-up or
software reboot. Write commands to the configuration
EEPROM are allowed at any time, unless the configura-
tion lock bit is set (see Table 15). The maximum cycle
time to write a single byte is 11ms (max).
Configuration Register Bank and EEPROM
The configuration registers can be directly modified
with the serial interface without modifying the EEPROM,
after the power-up procedure terminates and the con-
figuration EEPROM data has been loaded into the con-
figuration register bank. Use the write byte or block
write protocols to write directly to the configuration reg-
isters. Changes to the configuration registers are lost
upon power removal.
At device power-up, the register bank loads configura-
tion data from the EEPROM. Configuration data can be
directly altered in the register bank during application
development, allowing maximum flexibility. Transfer the
new configuration data byte-by-byte to the configura-
tion EEPROM with the write byte protocol. The next
device power-up or software reboot automatically loads
the new configuration (Table 16).
