MAX6876
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
22 ______________________________________________________________________________________
Outputs
GATE_
The MAX6876 features four GATE_ outputs to drive four
external n-channel FET gates. The following conditions
must be met before GATE_ begins enhancing the
external n-channel FET_:
1) All monitored inputs (IN1IN4) are above their
selected thresholds (0.5V to 5.5V)
2) At least one IN_ input or V
CC
is above 2.7V
3) Drive ENABLE high
4) TRKEN > 1.25V
At power-up mode, GATE_ voltages are enhanced con-
trol loops so all OUT_ voltages track together at a user-
selected slew rate. Each GATE_ is internally pulled up
to 5V above its relative IN_ voltage to fully enhance the
external n-channel FET when power-up is complete. In
sequencing/tracking mode, a gate delay timeout is
internally counted prior to the start of each control ramp
(see Figures 1 and 2 and Table 9).
FAULT
The MAX6876 offers an open-drain, active-low tracking
fault alarm (FAULT). FAULT asserts low when a power-
up phase is not completed within the specified fault
period or if tracking voltages fail by more than ±250mV.
For multiple MAX6876 applications, FAULT is an
input/output pin and communicates fault information
between master/slave devices. Connect all FAULT pins
in an ORed configuration to force simultaneous shut-
down on all MAX6876s (Table 10.) See the Typical
Application Circuit.
Power-Good Outputs (PG_)
The MAX6876 features four power-good (PG_) outputs.
PG_ outputs are open-drain and require external
pullups.
When the OUT_ output is within the selected percent-
age of the IN_ voltage range (V
TH_PG
), the correspond-
ing PG_ output goes high impedance. PG_ stays low
until the OUT_ voltage exceeds the programmable
V
TH_PG
threshold for more than t
POK
(Table 11).
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
000 gate-delay timer value = 25µs
001 gate-delay timer value = 12.5ms
010 gate-delay timer value = 25.0ms
011 gate-delay timer value = 50.0ms
100 gate-delay timer value = 100.0ms
101 gate-delay timer value = 200.0ms
110 gate-delay timer value = 400.0ms
0Fh 2Fh [7:5]
111 gate-delay timer value = 1600.0ms
Table 9. GATE-Delay Time Settings
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
[7:6]
Bit [7:6] 00 fault power-up timer value = 25ms
01 fault power-up timer value = 50ms
10 fault power-up timer value = 100ms
11 fault power-up timer value = 200ms
0Ah 2Ah
[5:4]
Bit [5:4] 00 fault power-down timer value = 25ms
01 fault power-down timer value = 50ms
10 fault power-down timer value = 100ms
11 fault power-down timer value = 200ms
Table 10. FAULT Power-Up and Power-Down Time Settings
MAX6876
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
______________________________________________________________________________________ 23
Bus Removal Output (REM)
The MAX6876 features an open-drain bus removal
(REM) output. REM signals when it is safe to remove
the card after a controlled track/sequence power-down
operation. To initiate a power-down, drive ENABLE low
or send an I
2
C power-down command. REM monitors
OUT_ and when any of the OUT_ voltages are above
the V
TH_PL
threshold, REM stays low. When all OUT_
outputs are below V
TH_PL
, REM goes high impedance.
Connect REM to an external pullup resistor/LED chain
to visually signal when it is safe to remove a powered
board from the bus.
In tracking mode when REM is used in master/slave
operations, connect all REM pins together. The com-
mon REM connection remains low if any OUT_ supply
is above the V
TH_PL
threshold.
Overcurrent Output (
OC
)
The open-drain, active-low OC output asserts low if an
overcurrent condition is detected in any selected channel
for longer than t
OC
. Overcurrent conditions are deter-
mined as a differential voltage between IN_ and OUT_.
OC monitoring begins only after supply tracking or
sequencing has been completed and is disabled during
power-down operation (Table 12).
Reset Output (
RESET
)
The reset output, RESET, is an open-drain output that
monitors the selected OUT_ voltages. The selected
OUT_ voltages must exceed their selected PG_ thresh-
olds for the selected reset timeout period (t
RP
) before
RESET is deasserted. A manual reset input (MR) can
assert RESET. RESET remains low while MR is low.
RESET remains low for the selected reset timeout peri-
od (t
RP
) after MR transitions from low to high (Table 13).
Synchronization Hold Output (
HOLD
)
The MAX6876 features an open-drain, active-low syn-
chronization alert output/input. HOLD communicates
synchronization status between master/slave devices in
multiple MAX6876 applications. When a slave device
detects a tracking problem with respect to the master
SYNCH signal, the slave asserts HOLD low. When
tracking is back under control, the slaves HOLD is
deasserted and goes high again. The HOLD output
remains asserted while selected tracking IN_ inputs are
below their selected thresholds (the slave device can
delay a tracking start until its inputs are at their required
stable voltage levels) or held low by the master when it
is counting the autoretry time after a detected fault con-
dition. Connect HOLD pins only to other MAX6876
HOLD pins.
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
00 IN4 to OUT4 power-good threshold = 95%
01 IN4 to OUT4 power-good threshold = 92.5%
10 IN4 to OUT4 power-good threshold = 90%
[7:6]
11 IN4 to OUT4 power-good threshold = 87.5%
00 IN3 to OUT3 power-good threshold = 95%
"01" IN3 to OUT3 power-good threshold = 92.5%
10 IN3 to OUT3 power-good threshold = 90%
11 IN3 to OUT3 power-good threshold = 87.5%
00 IN2 to OUT2 power-good threshold = 95%
01 IN2 to OUT2 power-good threshold = 92.5%
10 IN2 to OUT2 power-good threshold = 90%
11 IN2 to OUT2 power-good threshold = 87.5%
00 IN1 to OUT1 power-good threshold = 95%
01 IN1 to OUT1 power-good threshold = 92.5%
10 IN1 to OUT1 power-good threshold = 90%
10h 30h
[5:0]
11 IN1 to OUT1 power-good threshold = 87.5%
Table 11. PG Threshold Settings
MAX6876
EEPROM-Programmable, Quad,
Power-Supply Tracker/Sequencer Circuit
24 ______________________________________________________________________________________
ABP
ABP powers the analog circuitry. Bypass ABP to GND
with a 1µF ceramic capacitor installed as close to the
device as possible. Do not use ABP to provide power
to external circuitry.
Configuring the MAX6876
The MAX6876 factory-default configuration sets all reg-
isters to 00h. This device requires configuration before
full power is applied to the system. To configure the
MAX6876, first apply an input voltage greater than 2.7V
to one of IN1IN4 or V
CC
(see the Powering the
MAX6876 section). Next, transmit data with the serial
interface. Use the block write protocol to quickly config-
ure the device. Write to the configuration registers first,
to ensure the device is configured properly. After com-
pleting the setup procedure, use the read word proto-
col to read back the data from the configuration
registers. Lastly, use the write word protocol to write
this data to the EEPROM registers. After completing the
EEPROM register configuration, apply full power to the
system to begin normal operation. The nonvolatile
EEPROM stores the latest configuration upon removal
of power (Table 14).
Software Reboot
A command code of C4h initiates a software reboot. A
software reboot allows the user to restore the EEPROM
configuration to the volatile registers without cycling the
power supplies.
REGISTER
ADDRESS
EEPROM MEMORY
ADDRESS
BIT RANGE
DESCRIPTION
[7:6]
Bit [7:6] 00 IN4 to OUT4 overcurrent threshold = 97.5%
01 IN4 to OUT4 overcurrent threshold = 95%
10 IN4 to OUT4 overcurrent threshold = 92.5%
11 IN4 to OUT4 overcurrent threshold = 90%
Bit [5:4] 00 IN3 to OUT3 overcurrent threshold = 97.5%
01 IN3 to OUT3 overcurrent threshold = 95%
10 IN3 to OUT3 overcurrent threshold = 92.5%
11 IN3 to OUT3 overcurrent threshold = 90%
Bit [3:2] 00 IN2 to OUT2 overcurrent threshold = 97.5%
01 IN2 to OUT2 overcurrent threshold = 95%
10 IN2 to OUT2 overcurrent threshold = 92.5%
11 IN2 to OUT2 overcurrent threshold = 90%
0Dh 2Dh
[5:0]
Bit [1:0] 00 IN1 to OUT1 overcurrent threshold = 97.5%
01 IN1 to OUT1 overcurrent threshold = 95%
10 IN1 to OUT1 overcurrent threshold = 92.5%
11 IN1 to OUT1 overcurrent threshold = 90%
Bit [7:6] 00 overcurrent timer value = 12.5ms
01 overcurrent timer value = 50ms
10 overcurrent timer value = 100ms
11 overcurrent timer value = 200ms
Bit 5If 1, overcurrent monitoring on OUT1 is enabled
If 0, no overcurrent monitoring on OUT1
Bit 4If 1, overcurrent monitoring on OUT2 is enabled
If 0, no overcurrent monitoring on channel 1
Bit 3If 1, overcurrent monitoring on OUT3 is enabled
If 0, no overcurrent monitoring on OUT3
0Eh 2Eh [7:1]
Bit 2If 1, overcurrent monitoring on OUT4 is enabled
If 0, no overcurrent monitoring on OUT4
Table 12. OC Threshold Settings

MAX6876ETX+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Supervisory Circuits EEPROM-Prog Quad Power-Sup Sequence
Lifecycle:
New from this manufacturer.
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