MAX6876ETX+T Datasheet MAX6876ETX+T, MAX6876ETX+ | P25-P27

MAX6876

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

______________________________________________________________________________________ 25

SMBus/I

C-Compatible Serial Interface

The MAX6876 features an I

C/SMBus-compatible 2-

wire serial interface consisting of a serial data line

(SDA) and a serial clock line (SCL). SDA and SCL facili-

tate bidirectional communication between the

MAX6876 and the master device at clock rates up to

400kHz. Figure 10 shows the 2-wire interface timing

diagram. The MAX6876 is transmit/receive slave-only,

relying upon a master device to generate a clock sig-

nal. The master device (typically a microcontroller) initi-

ates a data transfer on the bus and generates SCL to

permit that transfer.

A master device communicates to the MAX6876 by

transmitting the proper address followed by command

and/or data words. Each transmit sequence is framed

by a START (S) or REPEATED START (SR) condition

and a STOP (P) condition. Each word transmitted over

the bus is 8 bits long and is always followed by an

acknowledge pulse.

SCL is a logic input, while SDA is an open-drain

input/output. SCL and SDA both require external pullup

resistors to generate the logic-high voltage. Use 4.7kΩ

for most applications.

Bit Transfer

Each clock pulse transfers one data bit. The data on

SDA must remain stable while SCL is high (Figure 11);

otherwise, the MAX6876 registers a START or STOP

condition (Figure 12) from the master. SDA and SCL

idle high when the bus is not busy.

Start and Stop Conditions

Both SCL and SDA idle high when the bus is not busy.

A master device signals the beginning of a transmis-

sion with a START (S) condition (Figure 8) by transition-

ing SDA from high to low while SCL is high. The master

device issues a STOP (P) condition (Figure 8) by transi-

tioning SDA from low to high while SCL is high. A STOP

condition frees the bus for another transmission. The

bus remains active if a REPEATED START condition is

generated, such as in the block read protocol (see

Figure 11).

Early STOP Conditions

The MAX6876 recognizes a STOP condition at any point

during transmission except if a STOP condition occurs in

the same high pulse as a START condition. This condi-

tion is not a legal I

C format; at least one clock pulse

must separate any START and STOP condition.

ADDRESS

EEPROM MEMORY

ADDRESS

BIT RANGE

DESCRIPTION

Bit 7—If 1, OUT1 also controls RESET

If 0, OUT1 does not control RESET

Bit 6—If 1, OUT2 also controls RESET

If 0, OUT2 does not control RESET

Bit 5—If 1, OUT3 also controls RESET

If 0, OUT3 does not control RESET

Bit 4—If 1, OUT4 also controls RESET

If 0, OUT4 does not control RESET

11h 31h [7:1]

Bit [3:1] “000” reset timer value = 25µs

“001” reset timer value = 12.5ms

“010” reset timer value = 25.0ms

“011” reset timer value = 50.0ms

“100” reset timer value = 100.0ms

“101” reset timer value = 200.0ms

“110” reset timer value = 400.0ms

“111” reset timer value = 1600.0ms

Table 13. Program RESET

MAX6876

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

26 ______________________________________________________________________________________

REGISTERS DESCRIPTIONS

Input Undervoltage Thresholds

(Registers 00h to 03h)

Input undervoltage thresholds (0.5V to 3.04V in 10mV increments or 1.0V to 5.5V in 20mV

increments). Each channel’s range is selected with register 08h.

Input Overvoltage Thresholds

(Registers 04h to 07h)

Input overvoltage thresholds (0.5V to 3.04V in 10mV increments or 1.0V to 5.5V in 20mV

increments). Each channel’s range is selected with register 08h.

Tracking/Sequencing Modes

Selects if outputs are to be sequenced or tracked. Sequencing/tracking modes are defined

by 4 bits for each OUT voltage of register 0Bh and 0Ch (see the Track/Sequence section).

Tracking/Sequencing

Power-Up/Down Slew Rate

Selectable output slew rate for power-up/down mode. Selected slew is overwritten during

tracking faults. Power-up/down slew rate is selected by bit [6:7] of register 12h.

Power-Up Delay Period

Power-up sequencing delay. Selects delay time for sequencing each supply.

Programmable delays are selected with bit [5:7] of register 0Fh.

Power-Down Sequence/Track

Behavior

Selectable power-down operation. Chooses if output voltages should be brought down in

the reverse sequence from power-up mode selections or if power supplies should be

simultaneously fast powered down (selected with bit 7 register 13h).

OUT Pulldown Enable

Selects if OUT_ should be internally pulled to GND when in fast shutdown or tracking fault

mode (selected with bit [6:3] register 13h).

Single/Multiple Device Application

Selects if the device will be used alone or in a master/slave application. If a single

application, the device can be operated in mixed sequencing/tracking modes. If multi-

device application, the device can be operated in tracking mode only (selected with bit

[7:6] register 09h).

00: single device 11: master device 01 or 10: slave device

Over cur r ent Thr eshol d

S el ects IN _- to- OU T_ thr eshol d vol tag e for over cur r ent m oni tor i ng for each channel ( r eg i ster 0D h) .

Power-Good Threshold

Selects IN_-to-OUT_ threshold voltage for power-good monitoring for each channel

(register 10h).

Overcurrent Assert Select S el ects w hi ch over cur r ent m oni tor s w i l l asser t the OC outp ut ( sel ected b y b i t [ 5:2] of r eg . 0E h) .

Overcurrent Filter Period

S el ects the fi l ter ti m e for the over cur r ent m oni tor s. O C w i l l not asser t unti l the over cur r ent

cond i ti on has exi sted l ong er than the sel ected fi l ter p er i od ( sel ected b y b i t [ 7:6] of r eg . 0E h) .

Fault Timeout Period

Selects the timeout period for sequencing/tracking completion. If sequencing/tracking

operation is not complete before the fault timeout period, a FAULT alert will be signaled

and all supplies will be powered down (selected by bit [7:4] of reg. 0Ah).

Fault Behavior

Selects how the device should operate during faults. Options include latch-off after fault or

autoretry after fault. Autoretry delay is selectable (selected by bit 5 of reg. 09h).

Reset Assert Select S el ects w hi ch O U T d etector s w i l l asser t the RE SE T outp ut ( sel ected b y b i t [ 7:4] of r eg . 11h) .

Reset Timeout Period Select Selects the reset timeout period (selected by bit [3:1] of reg. 11h).

Enable the Part with I

C Interface

Bit 0 and bit 1 of register 09h allows a micro to turn the MAX6876 on/off with the I

interface. While 09h[1] is 0, the part will ignore any enable command from I

C. If 09h[1] is

set to 1, then 09h[0] has to be 1 to enable the part to power on.

Table 14. Registers Summary

MAX6876

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

______________________________________________________________________________________ 27

Repeated START Conditions

A REPEATED START (SR) condition may indicate a

change of data direction on the bus. Such a change

occurs when a command word is required to initiate a

read operation (see Figure 12). SR may also be used

when the bus master is writing to several I

C devices

and does not want to relinquish control of the bus. The

MAX6876 serial interface supports continuous write

operations with or without an SR condition separating

them. Continuous read operations require SR condi-

tions because of the change in direction of data flow.

Acknowledge

The acknowledge bit (ACK) is the 9th bit attached to

any 8-bit data word. The receiving device always gen-

erates an ACK. The MAX6876 generates an ACK when

receiving an address or data by pulling SDA low during

the 9th clock period (Figure 13). When transmitting

data, such as when the master device reads data back

from the MAX6876, the device waits for the master

device to generate an ACK. Monitoring ACK allows for

detection of unsuccessful data transfers. An unsuc-

cessful data transfer occurs if the receiving device is

busy or if a system fault has occurred. In the event of

an unsuccessful data transfer, the bus master should

reattempt communication at a later time. The MAX6876

generates a NACK after the slave address during a

software reboot, while writing to the EEPROM, or when

receiving an illegal memory address.

STOP

CONDITION

REPEATED START

CONDITION

START

CONDITION

HIGH

LOW

SU:DAT

SU:STA

SU:STO

HD:STA

BUF

HD:STA

HD:DAT

SCL

SDA

START

CONDITION

Figure 10. Serial-Interface Timing Details

DATA LINE STABLE,

DATA VALID

SDA

SCL

CHANGE OF

DATA ALLOWED

Figure 11. Bit Transfer

START

CONDITION

SDA

SCL

STOP

CONDITION

Figure 12. Start and Stop Conditions

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39

MAX6876ETX+T

Mfr. #:

Buy MAX6876ETX+T

Manufacturer:

Maxim Integrated

Description:

Supervisory Circuits EEPROM-Prog Quad Power-Sup Sequence

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

MAX6876ETX+T

MAX6876ETX+T

Products related to this Datasheet