MAX6876ETX+T Datasheet MAX6876ETX+T, MAX6876ETX+ | P28-P30

MAX6876

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

28 ______________________________________________________________________________________

Slave Address

The MAX6876 slave address conforms to the following

table:

SA7–SA4 represent the standard 2-wire interface

address (1010) for devices with EEPROM. SA3 and

SA2 correspond to the A1 and A0 address inputs of the

MAX6876 (hardwired as logic low or logic high). SA0 is

a read/write flag bit (0 = write, 1 = read).

The A0 and A1 address inputs allow up to four

MAX6876s to connect to one bus. Connect A0 and A1

to GND or to HBP (see Figure 14).

Send Byte

The send byte protocol allows the master device to send

one byte of data to the slave device (see Figure 15). The

send byte presets a register pointer address for a sub-

sequent read or write. The slave sends a NACK instead

of an ACK if the master tries to send an address that is

not allowed. If the master sends C0h or C1h, the data is

ACK, because this could be the start of the write block

or read block. If the master sends a stop condition, the

internal address pointer does not change. If the master

sends C4h, this signifies a software reboot. The send

byte procedure follows:

1) The master sends a start condition.

2) The master sends the 7-bit slave address and a

write bit (low).

3) The addressed slave asserts an ACK on SDA.

4) The master sends an 8-bit data byte.

5) The addressed slave asserts an ACK on SDA.

6) The master sends a stop condition.

Write Byte/Word

The write byte/word protocol allows the master device

to write a single byte in the register bank, preset an

EEPROM (configuration or user) address for a subse-

quent read, or to write a single byte to the configuration

EEPROM (see Figure 15). The write byte/word proce-

dure follows:

1) The master sends a start condition.

2) The master sends the 7-bit slave address and a

write bit (low).

3) The addressed slave asserts an ACK on SDA.

4) The master sends an 8-bit command code.

5) The addressed slave asserts an ACK on SDA.

6) The master sends an 8-bit data byte.

7) The addressed slave asserts an ACK on SDA.

SCL

SDA BY

TRANSMITTER

SDA BY

RECEIVER

START

CONDITION

CLOCK PULSE FOR ACKNOWLEDGE

Figure 13. Acknowledge

SA7

(MSB)

SA6

SA5

SA4

SA3

SA2

SA1

SA0

(LSB)

1010

A1 A0

XR/W

X = Don’t care.

MAX6876

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

______________________________________________________________________________________ 29

8) The master sends a stop condition or sends another

8-bit data byte.

9) The addressed slave asserts an ACK on SDA.

10) The master sends a stop condition.

To write a single byte to the register bank, only the 8-bit

command code and a single 8-bit data byte are sent.

The command code must be in the range of 00h to 13h

to write on RAM or 20h to 33h to write on EEPROM. The

data byte is written to the register bank if the command

code is valid. The slave generates a NACK at step 5 if

the command code is invalid.

Block Write

The block write protocol allows the master device to

write a block of data (1 to 16 bytes) to the EEPROM or

to the register bank (see Figure 15). The destination

address must already be set by the send byte or write

byte protocol. If the number of bytes to be written caus-

es the address pointer to exceed 13h for the configura-

tion register (or 33h for the configuration EEPROM), the

address pointer stays at 13h (or 33h), overwriting this

memory address with the remaining bytes of data. The

last data byte sent is stored at register address 13h (or

33h). The block write procedure follows:

1) The master sends a start condition.

2) The master sends the 7-bit slave address and a

write bit (low).

3) The addressed slave asserts an ACK on SDA.

4) The master sends the 8-bit command code for

block write (83h).

5) The addressed slave asserts an ACK on SDA.

6) The master sends the 8-bit byte count (1 to 16

bytes), N.

7) The addressed slave asserts an ACK on SDA.

8) The master sends 8 bits of data.

9) The addressed slave asserts an ACK on SDA.

10) Repeat steps 8 and 9 N - 1 times.

11) The master generates a stop condition.

Block Read

The block read protocol allows the master device to

read a block of 16 bytes from the EEPROM or register

bank (see Figure 15). Read fewer than 16 bytes of data

by issuing an early STOP condition from the master, or

by generating a NACK with the master. The send byte

or write byte protocol predetermines the destination

address with a command code of C1h. The block read

procedure follows:

1) The master sends a start condition.

2) The master sends the 7-bit slave address and a

write bit (low).

3) The addressed slave asserts an ACK on SDA.

4) The master sends 8 bits of the block read com-

mand (C1h).

5) The slave asserts an ACK on SDA, unless busy.

SDA

SCL

MSB LSBSTART

XR/W

ACK

Figure 14. Slave Address

MAX6876

EEPROM-Programmable, Quad,

Power-Supply Tracker/Sequencer Circuit

30 ______________________________________________________________________________________

WRITE BYTE FORMAT

S ADDRESS

7 bits

SEND BYTE FORMAT

WR ACK DATA

8 bits

ACK P

Data Byte–presets the

internal address pointer.

WRITE WORD FORMAT

S ADDRESS WR ACK ACK ACK ACKCOMMAND DATA DATA P

7 bits 8 bits 8 bits 8 bits

Slave Address–

equivalent to chip-

select line of a 3-

wire interface.

Write Address of

the register you are

writing to.

Data Byte–

Data goes into

the register set by

the command.

BLOCK WRITE FORMAT

S ADDRESS WR

ACK COMMAND ACK

BYTE

COUNT= N

ACK

DATA BYTE

ACK

DATA BYTE

...

ACK

DATA BYTE

ACK P

7 bits 8 bits 8 bits 8 bits 8 bits

Slave Address–

equivalent to chip-

select line of a 3-

wire interface.

Command Byte–

prepares device

for block

operation.

Data Byte–data goes into the register set by the

command byte.

BLOCK READ FORMAT

S ADDRESS WR ACK COMMAND ACK SR ADDRESS WR ACK

8 bits

BYTE

COUNT= 16

ACK

DATA BYTE

ACK

DATA BYTE

...

ACK

DATA BYTE

ACK P

7 bits 8 bits 7 bits 10h 8 bits8 bits 8 bits

Slave Address–

equivalent to chip-

select line of a 3-

wire interface.

Command Byte–

prepares device

for block

operation.

Slave Address–

equivalent to chip-

select line of a 3-

wire interface.

Data Byte–data goes into the register set by the

command byte.

S = Start condition.

P = Stop condition.

Shaded = Slave transmission.

SR = Repeated start condition.

Slave Address–

equivalent to chip-

select line of a 3-

wire interface.

S ADDRESS WR ACK COMMAND ACK DATA ACK P

7 bits 8 bits 8 bits

Slave Address–

equivalent to chip-

select line of a 3-

wire interface.

Command Byte–

selects register

you are writing to.

Data Byte–data goes into the

Data Byte–

Data goes into

the next register set by

the command.

Figure 15. SMBus/I

C Protocols

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39

MAX6876ETX+T

Mfr. #:

Buy MAX6876ETX+T

Manufacturer:

Maxim Integrated

Description:

Supervisory Circuits EEPROM-Prog Quad Power-Sup Sequence

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

MAX6876ETX+T

MAX6876ETX+T

Products related to this Datasheet