IDT723612L15PF Datasheet IDT723612L20PQF, IDT723612L15PF, IDT723612L15PQF | P10-P12

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723612

CMOS SYNCBiFIFO

64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

FEBRUARY 13, 2009

TABLE 3 — PORT-B ENABLE FUNCTION TABLE

SIGNAL DESCRIPTIONS

RESET

The IDT723612 is reset by taking the Reset (RST) input LOW for at least

four port-A clock (CLKA) and four port-B Clock (CLKB) LOW-to-HIGH

transitions. The Reset input can switch asynchronously to the clocks. A device

reset initializes the internal read and write pointers of each FIFO and forces

the Full Flags (FFA, FFB) LOW, the Empty Flags (EFA, EFB) LOW, the Almost-

Empty flags (AEA, AEB) LOW and the Almost-Full flags (AFA, AFB) HIGH. A

reset also forces the Mailbox Flags (MBF1, MBF2) HIGH. After a reset, FFA

is set HIGH after two LOW-to-HIGH transitions of CLKA and FFB is set HIGH

after two LOW-to-HIGH transitions of CLKB. The device must be reset after

power up before data is written to its memory.

A LOW-to-HIGH transition on the RST input loads the Almost-Full and

Almost-Empty registers (X) with the values selected by the Flag Select (FS0,

FS1) inputs. The values that can be loaded into the registers are shown in

Table 1.

FIFO WRITE/READ OPERATION

The state of port-A data A0-A35 outputs is controlled by the port-A Chip

Select (CSA) and the port-A Write/Read select (W/RA). The A0-A35 outputs

are in the high-impedance state when either CSA or W/RA is HIGH. The A0-

A35 outputs are active when both CSA and W/RA are LOW.

Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH

transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA

is LOW, and FFA is HIGH. Data is read from FIFO2 to the A0-A35 outputs by

a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA is

HIGH, MBA is LOW, and EFA is HIGH (see Table 2).

The port-B control signals are identical to those of port A. The state of the

port-B data (B0-B35) outputs is controlled by the port-B Chip Select (CSB) and

the port-B Write/Read select (W/RB). The B0-B35 outputs are in the high-

impedance state when either CSB or W/RB is HIGH. The B0-B35 outputs are

active when both CSB and W/RB are LOW.

Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH

transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is

LOW, and FFB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by

a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is

HIGH, MBB is LOW, and EFB is HIGH (see Table 3).

CSB W/RB ENB MBB CLKB B0-B35 Outputs Port Functions

HXXXX In High-Impedance State None

L H L X X In High-Impedance State None

LHHL↑ In High-Impedance State FIFO2 Write

LHHH↑ In High-Impedance State Mail2 Write

LLLLX Active, FIFO1 Output Register None

LLHL↑ Active, FIFO1 Output Register FIFO1 read

L L L H X Active, Mail1 Register None

LLHH↑ Active, Mail1 Register Mail1 Read (Set MBF1 HIGH)

CSA W/RA ENA MBA CLKA A0-A35 Outputs Port Functions

HXXXX In High-Impedance State None

L H L X X In High-Impedance State None

LHHL↑ In High-Impedance State FIFO1 Write

LHHH↑ In High-Impedance State Mail1 Write

LLLLX Active, FIFO2 Output Register None

LLHL↑ Active, FIFO2 Output Register FIFO2 Read

L L L H X Active, Mail2 Register None

LLHH↑ Active, Mail2 Register Mail2 Read (Set MBF2 HIGH)

TABLE 2 — PORT-A ENABLE FUNCTION TABLE

ALMOST-FULL AND

FS1 FS0 RST ALMOST-EMPTY FLAG

OFFSET REGISTER (X)

HH↑ 16

HL↑ 12

LH↑ 8

LL↑ 4

TABLE 1 — FLAG PROGRAMMING

IDT723612

CMOS SYNCBiFIFO

64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

FEBRUARY 13, 2009

The setup and hold time constraints to the port clocks for the port Chip Selects

(CSA, CSB) and Write/Read selects (W/RA, W/RB) are only for enabling write

and read operations and are not related to high-impedance control of the data

outputs. If a port enable is LOW during a clock cycle, the port chip select and

write/read select may change states during the setup and hold time window

of the cycle.

SYNCHRONIZED FIFO FLAGS

Each FIFO is synchronized to its port clock through two flip-flop stages. This

is done to improve flag reliability by reducing the probability of metastable

events on the output when CLKA and CLKB operate asynchronously to one

another. EFA, AEA, FFA, and AFA are synchronized by CLKA. EFB, AEB,

FFB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship

of each port flag to FIFO1 and FIFO2.

EMPTY FLAGS (EFA, EFB)

The Empty Flag of a FIFO is synchronized to the port clock that reads

data from its array. When the Empty Flag is HIGH, new data can be read to

the FIFO output register. When the Empty Flag is LOW, the FIFO is empty and

attempted FIFO reads are ignored.

The read pointer of a FIFO is incremented each time a new word is

clocked to the output register. The state machine that controls an Empty Flag

monitors a write-pointer and read-pointer comparator that indicates when the

FIFO SRAM status is empty, empty+1, or empty+2. A word written to a FIFO

can be read to the FIFO output register in a minimum of three cycles of the Empty

Flag synchronizing clock. Therefore, an Empty Flag is LOW if a word in memory

is the next data to be sent to the FIFO output register and two cycles of the port

clock that reads data from the FIFO have not elapsed since the time the word

was written. The Empty Flag of the FIFO is set HIGH by the second LOW-to-

HIGH transition of the synchronizing clock, and the new data word can be read

to the FIFO output register in the following cycle.

A LOW-to-HIGH transition on an Empty Flag synchronizing clock begins the

first synchronization cycle of a write if the clock transition occurs at time tSKEW1

or greater after the write. Otherwise, the subsequent clock cycle can be the first

synchronization cycle.

FULL FLAG (FFA, FFB)

The Full Flag of a FIFO is synchronized to the port clock that writes data to

its array. When the Full Flag is HIGH, a memory location is free in the SRAM

to receive new data. No memory locations are free when the Full Flag is LOW

and attempted writes to the FIFO are ignored.

Synchronized Synchronized

to CLKB to CLKA

EFB AEB AFA FFA

0LLHH

1 to X H L H H

(X+1) to [64–(X+1)] H H H H

(64–X) to 63 H H L H

64 H H L L

Synchronized Synchronized

to CLKB to CLKA

EFA AEA AFB FFB

0LLHH

1 to X H L H H

(X+1) to [64–(X+1)] H H H H

(64–X) to 63 H H L H

64 H H L L

TABLE 4 — FIFO1 FLAG OPERATION TABLE 5 — FIFO2 FLAG OPERATION

NOTE:

1. X is the value in the Almost-Empty flag and Almost-Full flag offset register.

Each time a word is written to a FIFO, the write pointer is incremented. The

state machine that controls a Full Flag monitors a write-pointer and read pointer

comparator that indicates when the FIFO SRAM status is full, full-1, or full-2.

From the time a word is read from a FIFO, the previous memory location is

ready to be written in a minimum of three cycles of the Full Flag synchronizing

clock. Therefore, a Full Flag is LOW if less than two cycles of the Full Flag

synchronizing clock have elapsed since the next memory write location has

been read. The second LOW-to-HIGH transition on the Full Flag synchroni-

zation clock after the read sets the Full Flag HIGH and the data can be written

in the following clock cycle.

A LOW-to-HIGH transition on a Full Flag synchronizing clock begins the

first synchronization cycle of a read if the clock transition occurs at time tSKEW1

or greater after the read. Otherwise, the subsequent clock cycle can be the first

synchronization cycle.

ALMOST EMPTY FLAGS (AEA, AEB)

The Almost-Empty flag of a FIFO is synchronized to the port clock that

reads data from its array. The state machine that controls an Almost-Empty flag

monitors a write-pointer comparator that indicates when the FIFO SRAM status

is almost-empty, almost-empty+1, or almost-empty+2. The almost-empty state

is defined by the value of the Almost-Full and Almost-Empty Offset register (X).

This register is loaded with one of four preset values during a device reset (see

Reset above). An Almost-Empty flag is LOW when the FIFO contains X or less

words in memory and is HIGH when the FIFO contains (X+1) or more words.

Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing clocks

are required after a FIFO write for the Almost-Empty flag to reflect the new level

of fill. Therefore, the Almost-Empty flag of a FIFO containing (X+1) or more

words remains LOW if two cycles of the synchronizing clock have not elapsed

since the write that filled the memory to the (X+1) level. An Almost-Empty flag

is set HIGH by the second LOW-to-HIGH transition of the synchronizing clock

after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH

transition of an Almost-Empty flag synchronizing clock begins the first synchro-

nization cycle if it occurs at time tSKEW2 or greater after the write that fills the FIFO

to (X+1) words. Otherwise, the subsequent synchronizing clock cycle can be

the first synchronization cycle (see Figure 7 and 8).

ALMOST FULL FLAGS (AFA, AFB)

The Almost-Full flag of a FIFO is synchronized to the port clock that writes

data to its array. The state machine that controls an Almost-Full flag monitors

a write-pointer and read-pointer comparator that indicates when the FIFO

Number of Words

in the FIFO1

(1)

Number of Words

in the FIFO1

(1)

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723612

CMOS SYNCBiFIFO

64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

FEBRUARY 13, 2009

SRAM status is almost-full, almost-full-1, or almost-full-2. The almost-full state

is defined by the value of the Almost-Full and Almost-Empty Offset register (X).

This register is loaded with one of four preset values during a device reset (see

Reset above). An Almost-Full flag is LOW when the FIFO contains (64-X) or

more words in memory and is HIGH when the FIFO contains [64-(X+1)] or

less words.

Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are

required after a FIFO read for the Almost-Full flag to reflect the new level of fill.

Therefore, the Almost-Full flag of a FIFO containing [64-(X+1)] or less words

remains LOW if two cycles of the synchronizing clock have not elapsed since

the read that reduced the number of words in memory to [64-(X+1)]. An Almost-

Full flag is set HIGH by the second LOW-to-HIGH transition of the synchronizing

clock after the FIFO read that reduces the number of words in memory to [64-

(X+1)]. A second LOW-to-HIGH transition of an Almost-Full flag synchronizing

clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater

after the read that reduces the number of words in memory to [64-(X+1)].

Otherwise, the subsequent synchronizing clock cycle can be the first synchro-

nization cycle (see Figure 14 and 15).

MAILBOX REGISTERS

Each FIFO has a 36-bit bypass register to pass command and control

information between port A and port B without putting it in queue. The Mailbox

select (MBA, MBB) inputs choose between a mail register and a FIFO for a

port data transfer operation. A LOW-to-HIGH transition on CLKA writes A0-

A35 data to the mail1 register when a port-A write is selected by CSA, W/RA,

and ENA and MBA HIGH. A LOW-to-HIGH transition on CLKB writes B0-B35

data to the mail2 register when a port-B write is selected by CSB, W/RB, and

ENB and MBB is HIGH. Writing data to a mail register sets the corresponding

flag (MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while

the mail flag is LOW.

When a port's data outputs are active, the data on the bus comes from the

FIFO output register when the port Mailbox-select input (MBA, MBB) is LOW

and from the mail register when the port mailbox-select input is HIGH. The Mail1

a port-B read is selected by CSB, W/RB, and ENB and MBB is HIGH. The Mail2

port-A read is selected by CSA, W/RA, and ENA and MBA is HIGH. The data

in a mail register remains intact after it is read and changes only when new data

is written to the register.

PARITY CHECKING

The port-A inputs (A0-A35) and port-B inputs (B0-B35) each have four

parity trees to check the parity of incoming (or outgoing) data. A parity failure

on one or more bytes of the input bus is reported by a LOW level on the port

Parity Error Flag (PEFA, PEFB). Odd or even parity checking can be selected,

and the Parity Error Fags can be ignored if this feature is not desired.

Parity status is checked on each input bus according to the level of the Odd/

Even parity (ODD/EVEN) select input. A parity error on one or more bytes of

a port is reported by a LOW level on the corresponding port Parity Error Flag

(PEFA, PEFB) output. Port-A bytes are arranged as A0-A8, A9-A17, A18-

A26, and A27-A35 with the most significant bit of each byte used as the parity

bit. Port-B bytes are arranged as B0-B8, B9-B17, B18-B26, and B27-B35,

with the most significant bit of each byte used as the parity bit. When odd/even

parity is selected, a port parity error flag (PEFA, PEFB) is LOW if any byte on

the port has an odd/even number of LOW levels applied to the bits.

The four parity trees used to check the A0-A35 inputs are shared by the mail2

When a port-A read from the mail2 register with parity generation is selected

with W/RA LOW, CSA LOW, ENA HIGH, MBA HIGH, and PGA HIGH, the port-

A Parity Error Flag (PEFA) is held HIGH regardless of the levels applied to

the A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs

are shared by the mail1 register when parity generation is selected for port-

B reads (PGB = HIGH). When a port-B read from the mail1 register with parity

generation is selected with W/RB LOW, CSB LOW, ENB HIGH, MBB HIGH,

and PGB HIGH, the port-B parity error flag (PEFB) is held HIGH regardless

of the levels applied to the B0-B35 inputs.

PARITY GENERATION

A HIGH level on the port-A Parity Generate select (PGA) or port-B Parity

Generate select (PGB) enables the IDT723612 to generate parity bits for

port reads from a FIFO or mailbox register. Port-A bytes are arranged as A0-

A8, A9-A17, A18-26, and A27-A35, with the most significant bit of each byte

used as the parity bit. Port-B bytes are arranged as B0-B8, B9-B17, B18-B26,

and B27-B35, with the most significant bit of each byte used as the parity bit.

A write to a FIFO or mail register stores the levels applied to all thirty-six inputs

regardless of the state of the Parity Generate select (PGA, PGB) inputs. When

data is read from a port with parity generation selected, the lower eight bits of

each byte are used to generate a parity bit according to the level on the ODD/

EVEN select. The generated parity bits are substituted for the levels originally

written to the most significant bits of each byte as the word is read to the data

outputs.

Parity bits for FIFO data are generated after the data is read from SRAM

and before the data is written to the output register. Therefore, the port-A parity

generate select (PGA) and Odd/Even parity select (ODD/EVEN) have setup

and hold time constraints to the port-A Clock (CLKA) and the port-B Parity

Generate select (PGB) and ODD/EVEN have setup and hold-time constraints

to the port-B Clock (CLKB). These timing constraints only apply for a rising clock

edge used to read a new word to the FIFO output register.

The circuit used to generate parity for the mail1 data is shared by the port-

B bus (B0-B35) to check parity and the circuit used to generate parity for the

mail2 data is shared by the port-A bus (A0-A35) to check parity. The shared

parity trees of a port are used to generate parity bits for the data in a mail register

when the port Write/Read select (W/RA, W/RB) input is LOW, the port mail select

(MBA, MBB) input is HIGH, Chip Select (CSA, CSB) is LOW, Enable (ENA,

ENB) is HIGH, and port Parity Generate select (PGA, PGB) is HIGH.

Generating parity for mail register data does not change the contents of the

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

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