1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising
CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Figure 7.
EFBEFB
EFBEFB
EFB
Flag Timing and First Data Read when FIFO1 is Empty
17
IDT723612
CMOS SYNCBiFIFO
TM
64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009
CSB
W/RB
MBB
FFB
B0 - B35
CLKA
EFA
CSA
W/RA
MBA
ENB
ENA
A0 -A35
CLKB
12
3136 drw11
t
CLKH
t
CLKL
t
CLK
t
ENS3
t
ENS2
t
ENH3
t
ENH2
t
DS
t
DH
t
SKEW1
t
CLK
t
CLKL
t
ENS2
t
ENH2
t
A
W1
FIFO2 Empty
LOW
HIGH
LOW
LOW
LOW
t
CLKH
W1
HIGH
(1)
t
REF
t
REF
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Figure 8.
EFAEFA
EFAEFA
EFA
Flag Timing and First Data Read when FIFO2 is Empty
18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723612
CMOS SYNCBiFIFO
TM
64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
FEBRUARY 13, 2009
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.
Figure 9.
FFAFFA
FFAFFA
FFA
Flag Timing and First Available Write when FIFO1 is Full
