13
IDT723612
CMOS SYNCBiFIFO
TM
64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009
Figure 2. Device Reset Loading the X Register with the Value of Eight
CLKA
RST
FFA
FFB
EFB
AEA
CLKB
EFA
FS1,FS0
3136 drw05
t
RSTS
t
RSTH
t
FSH
t
FSS
t
WFF
t
WFF
t
WFF
0,1
t
REF
t
REF
t
PAE
t
PAF
AFA
MBF1,
MBF2
AEB
AFB
t
RSF
t
PAE
t
PAF
t
WFF
14
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723612
CMOS SYNCBiFIFO
TM
64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
FEBRUARY 13, 2009
Figure 4. Port-B Write Cycle Timing for FIFO2
NOTE:
1. Written to FIFO1.
3136 drw06
CLKA
FFA
ENA
A0 - A35
MBA
CSA
W/RA
t
CLKH
t
CLKL
t
CLK
t
ENS1
t
ENS1
t
ENS3
t
ENS2
t
DS
t
ENH1
t
ENH1
t
ENH3
t
ENH2
t
DH
W1
(1)
W2
(1)
t
ENS2
t
ENH2
t
ENH2
t
ENS2
No Operation
ODD/
EVEN
PEFA
Valid Valid
t
PDPE
t
PDPE
HIGH
Figure 3. Port-A Write Cycle Timing for FIFO1
3136 drw07
CLKB
FFB
ENB
B0 - B35
MBB
CSB
W/RB
t
CLKH
t
CLKL
t
CLK
t
ENS1
t
ENS1
t
ENS3
t
ENS2
t
DS
t
ENH1
t
ENH1
t
ENH3
t
ENH2
t
DH
W1
(1)
W2
(1)
t
ENS2
t
ENH2
t
ENH2
t
ENS2
No Operation
ODD/
EVEN
PEFB
Valid Valid
t
PDPE
t
PDPE
HIGH
NOTE:
1. Written to FIFO2.
15
IDT723612
CMOS SYNCBiFIFO
TM
64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009
3136 drw08
CLKB
EFB
ENB
B0 - B35
MBB
CSB
W/RB
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
A
t
MDV
t
EN
t
A
t
ENS2
t
ENH2
t
ENS2
t
ENH2
Previous Data
Word 1 Word 2
(1)
(1)
(1)
t
ENH2
No Operation
PGB,
ODD/
EVEN
HIGH
t
PGH
t
PGH
t
DIS
t
PGS
t
PGS
Figure 6. Port-A Read Cycle Timing for FIFO2
NOTE:
1. Read from FIFO1.
Figure 5. Port-B Read Cycle Timing for FIFO1
NOTE:
1. Read from FIFO2.
3136 drw09
CLKA
EFA
ENA
A0 - A35
MBA
CSA
W/RA
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
A
t
MDV
t
EN
t
A
t
ENS2
t
ENH2
t
ENS2
t
ENH2
Previous Data
Word 1 Word 2
(1)
(1)
(1)
t
ENH2
t
DIS
No Operation
PGA,
ODD/
EVEN
HIGH
t
PGH
t
PGH
t
PGS
t
PGS

IDT723612L15PF

Mfr. #:
Manufacturer:
Description:
IC FIFO 64X36X2 15NS 120QFP
Lifecycle:
New from this manufacturer.
Delivery:
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