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IDT723612L15PF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
22
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723612
CMOS SYNCBiFIFO
TM
64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
FEBRUARY 13, 2009
Figure 17. ODD/
EVENEVEN
EVENEVEN
EVEN
W/
RR
RR
R
A, MBA, and PGA to
PEFAPEFA
PEFAPEFA
PEFA
Timing
NOTE:
1. Port-A parity generation off (PGA = LOW).
Figure 16. Timing for Mail2 Register and
MBF2MBF2
MBF2MBF2
MBF2
Flag
NOTE:
1. ENA is HIGH, and CSA is LOW.
W1 (Remains valid in Mail2 Register after read)
3136 drw20
ODD/
EVEN
PEFA
PGA
MBA
W/RA
Valid Valid Valid Valid
t
POPE
t
PEPE
t
POPE
t
PEPE
23
IDT723612
CMOS SYNCBiFIFO
TM
64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009
3136 drw21
ODD/
EVEN
PEFB
PGB
MBB
W/RB
Valid Valid
Valid Valid
tPOPE
tPEPE
tPOPE
tPEPE
Figure 18. ODD/
EVENEVEN
EVENEVEN
EVEN
W/
RR
RR
R
B, MBB, and PGB to
PEFBPEFB
PEFBPEFB
PEFB
Timing
NOTE:
1. ENB is HIGH, and CSB is LOW.
Figure 20. Parity Generation Timing when Reading from Mail1 Register
NOTE:
1. ENB is HIGH.
3136 drw22
ODD/
EVEN
A8, A17,
A26, A35
PGA
MBA
W/RA
Mail2
Data
Generated Parity
Generated Parity
Mail2 Data
CSA
LOW
t
EN
t
PEPB
t
POPB
t
PEPB
t
MDV
Figure 19. Parity Generation Timing when Reading from Mail2 Register
NOTE:
1. ENA is HIGH.
3136 drw23
ODD/
EVEN
B8, B17,
B26, B35
PGB
MBB
W/RB
Mail1
Data
Generated Parity
Generated Parity
Mail1 Data
CSB
LOW
t
EN
t
PEPB
t
POPB
t
PEPB
t
MDV
24
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723612
CMOS SYNCBiFIFO
TM
64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
FEBRUARY 13, 2009
Figure 21. Load Circuit and Voltage Waveforms
NOTE:
1. Includes probe and jig capacitance.
3136 drw24
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
30 pF
1.1 k
Ω
5 V
680
Ω
LOAD CIRCUIT
3 V
GND
Timing
Input
Data,
Enable
Input
GND
3 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3 V
GND
GND
3 V
1.5 V
1.5 V
1.5 V
1.5 V
t
W
Output
Enable
Low-Level
Output
High-Level
Output
3 V
OL
GND
3 V
1.5 V
1.5 V
1.5 V
1.5 V
≈
OH
OV
≈
GND
OH
OL
1.5 V
1.5 V
1.5 V
1.5 V
Input
In-Phase
Output
High-Level
Input
Low-Level
Input
V
V
V
V
1.5 V
3 V
t
S
t
h
t
PLZ
t
PHZ
t
PZL
t
PZH
t
PD
t
PD
(1)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

IDT723612L15PF

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Manufacturer:
Description:
IC FIFO 64X36X2 15NS 120QFP
Lifecycle:
New from this manufacturer.
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