19
IDT723612
CMOS SYNCBiFIFO
TM
64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).
Figure 11. Timing for
AEBAEB
AEBAEB
AEB
when FIFO1 is Almost Empty
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.
Figure 10.
FFBFFB
FFBFFB
FFB
Flag Timing and First Available Write when FIFO2 is Full
CSA
EFA
MBA
ENA
A0 - A35
CLKA
FFB
CLKB
CSB
3136 drw13
W/RB
12
B0 - B35
MBB
ENB
t
ENS2
t
ENH2
t
ENS3
t
ENS2
t
DS
t
ENH3
t
ENH2
t
DH
To FIFO2
Previous Word in FIFO2 Output Register
Next Word From FIFO2
LOW
W/RA
LOW
LOW
HIGH
LOW
HIGH
FIFO2 Full
t
CLK
t
CLKH
t
CLKL
t
A
t
SKEW1
(1)
t
CLK
t
CLKH
t
CLKL
t
WFF
t
WFF
AEB
CLKA
ENB
3136 drw14
ENA
CLKB
2
1
tENS2
tENH2
tENS2
tENH2
X Word in FIFO1 (X+1) Words in FIFO1
tSKEW2
(1)
tPAE tPAE
20
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723612
CMOS SYNCBiFIFO
TM
64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
FEBRUARY 13, 2009
AEA
CLKB
ENA
3136 drw15
ENB
CLKA
2
1
t
ENS2
t
ENH2
t
ENS2
t
ENH2
(X+1) Words in FIFO2
X Words in FIFO2
t
SKEW2
(1)
t
PAE
t
PAE
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising
CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).
Figure 12. Timing for
AEAAEA
AEAAEA
AEA
when FIFO2 is Almost Empty
AFB
CLKB
ENA
3136 drw17
ENB
CLKA
12
t
ENS2
t
ENH2
t
ENS2
t
ENH2
[64-(X+1)] Words in FIFO2
(64-X) Words in FIFO2
t
PAF
t
SKEW2
(1)
t
PAF
Figure 14. Timing for
AFBAFB
AFBAFB
AFB
when FIFO2 is Almost Full
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising
CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).
Figure 13. Timing for
AFAAFA
AFAAFA
AFA
when FIFO1 is Almost Full
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising
CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).
AFA
CLKA
ENB
3136 drw16
ENA
CLKB
12
t
ENS2
t
ENH2
t
ENS2
t
ENH2
[64-(X+1)] Words in FIFO1
(64-X) Words in FIFO1
t
PAF
t
SKEW2
(1)
t
PAF
21
IDT723612
CMOS SYNCBiFIFO
TM
64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009
NOTE:
1. Port-B parity generation off (PGB = LOW).
Figure 15. Timing for Mail1 Register and
MBF1MBF1
MBF1MBF1
MBF1
Flag
3136 drw18
CLKA
ENA
A0 - A35
MBA
CSA
W/RA
CLKB
MBF1
CSB
MBB
ENB
B0 - B35
W/RB
W1
tENS1
tENH1
tDH
tEN
tENH2
W1 (Remains valid in Mail1 Register after read)
FIFO1 Output Register
tENS1
tENH1
tENS1 tENH1
tENS1 tENH1
tDS
tPMFtPMF
tENS2
tMDV
tPMR
tDIS

IDT723612L15PF

Mfr. #:
Manufacturer:
Description:
IC FIFO 64X36X2 15NS 120QFP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union