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IDT723612L15PF

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7
IDT723612
CMOS SYNCBiFIFO
TM
64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009
CALCULATING POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT723612 with CLKA and CLKB set
to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize
the graph to a zero-capacitance load. Once the capacitance load per data-output channel is known, the power dissipation can be calculated with the equation
below.
With ICC(f) taken from Figure 1, the maximum power dissipation (PD) of the IDT723612 may be calculated by:
PD = VCC x ICC(f) + Σ(CL x VCC x (VOH - VOL) x fo)
where:
CL = output capacitance load
fo = switching frequency of an output
VOH = output HIGH level voltage
VOL = output LOW level voltage
When no reads or writes are occurring on the IDT723612, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is
calculated by:
PT = VCC x fS x 0.290 mA/MHz
010 203040 50 60 80
0
50
100
150
200
250
300
350
400
VCC = 5.0V
fS ⎯ Clock Frequency ⎯ MHz
ICC(f) Supply Current mA
fdata = 1/2 fS
TA= 25°C
C
L = 0 pF
3136 drw04
70
VCC = 4.5V
VCC = 5.5V
Figure 1. Typical Characteristics: Supply Current vs Clock Frequency
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723612
CMOS SYNCBiFIFO
TM
64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
FEBRUARY 13, 2009
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
Commercial Com’l & Ind’l
(1)
IDT723612L15 IDT723612L20
Symbol Parameter Min. Max. Min. Max. Unit
fS Clock Frequency, CLKA or CLKB – 66.7 – 50 MHz
tCLK Clock Cycle Time, CLKA or CLKB 15 – 20 – ns
tCLKH Pulse Duration, CLKA and CLKB HIGH 6 – 8 – ns
tCLKL Pulse Duration, CLKA and CLKB LOW 6 – 8 – ns
tDS Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑ 4– 5–ns
tENS1 Setup Time, CSA, W/RA before CLKA↑; CSB, W/RB before CLKB↑ 6– 6–ns
tENS2 Setup Time, ENA, before CLKA↑; ENB before CLKB↑ 4– 5–ns
tENS3 Setup Time, MBA before CLKA↑: MBB before CLKB↑ 4– 5–ns
tPGS Setup Time, ODD/EVEN and PGA before CLKA↑; ODD/EVEN and PGB 4 – 5 – ns
before CLKB↑
(2 )
tRSTS Setup Time, RST LOW before CLKA↑ or CLKB↑
(3)
5– 6–ns
tFSS Setup Time, FS0/FS1 before RST HIGH 5 – 6 – ns
tDH Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑ 2.5 – 2.5 – ns
tENH1 Hold Time, CSA W/RA after CLKA↑; CSB, W/RB after CLKB↑ 2– 2–ns
tENH2 Hold Time, ENA, after CLKA↑; ENB after CLKB↑ 2.5 – 2.5 – ns
tENH3 Hold Time, MBA after CLKA↑; MBB after CLKB↑ 1– 1–ns
tPGH Hold Time, ODD/EVEN and PGA after CLKA↑; ODD/EVEN and PGB 1 – 1 – ns
after CLKB↑
(2 )
tRSTH Hold Time, RST LOW after CLKA↑ or CLKB↑
(3)
5– 6–ns
tFSH Hold Time, FS0 and FS1 after RST HIGH 4 – 4 – ns
tSKEW1
(4)
Skew Time, between CLKA↑ and CLKB↑ for EFA, EFB, FFA, and FFB 8– 8–ns
tSKEW2
(4)
Skew Time, between CLKA↑ and CLKB↑ For AEA, AEB, AFA, and AFB 14 – 16 – ns
NOTES:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Only applies for a clock edge that does a FIFO read.
3. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)
9
IDT723612
CMOS SYNCBiFIFO
TM
64 x 36 x 2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF
Commercial Com’l & Ind’l
(1)
IDT723612L15 IDT723612L20
Symbol Parameter Min. Max. Min. Max. Unit
tA Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35 2 10 2 12 ns
tWFF Propagation Delay Time, CLKA↑ to FFA and CLKB↑ to FFB 210212ns
tREF Propagation Delay Time, CLKA↑ to EFA and and CLKB↑ to EFB 210212ns
tPAE Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB 210212ns
tPAF Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB 210212ns
tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and CLKB↑ to 1 9 1 12 ns
MBF2 LOW or MBF1 HIGH
tPMR Propagation Delay Time, CLKA↑ to B0-B35
(2)
and CLKB↑ to A0-A35
(3)
311313ns
tMDV Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 valid 1 11 1 11.5 ns
tPDPE Propagation Delay Time, A0-A35 valid to PEFA valid; B0-B35 valid to PEFB valid 3 10 3 11 ns
tPOPE Propagation Delay Time, ODD/EVEN to PEFA and PEFB 311312ns
tPOPB
(4)
Propagation Delay Time, ODD/EVEN to parity bits (A8, A17, A26, A35) and 2 11 2 12 ns
(B8, B17, B26, B35)
tPEPE Propagation Delay Time, W/RA, CSA, ENA, MBA or PGA to PEFA; W/RB, CSB, 111112ns
ENB, MBB, PGB to PEFB
tPEPB
(4)
Propagation Delay Time, W/RA, CSA, ENA, MBA or PGA to parity bits ( A8, A17, A26, A35); 3 12 3 13 ns
W/RB, CSB, bits (B8, B17, B26, B35) ENB, MBB or PGB to parity
tRSF Propagation Delay Time, RST to (AEA, AEB) LOW and (AFA, AFB, MBF1, MBF2) 115120ns
HIGH
tEN Enable Time, CSA and W/RA LOW to A0-A35 active and CSB LOW and W/RB HIGH 2 10 2 12 ns
to B0-B35 active
tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high impedance and CSB HIGH 1 8 1 9 ns
or W/RB LOW to B0-B35 at high impedance.
NOTES:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
3 Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
4. Only applies when reading data from a mail register.
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)
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IDT723612L15PF

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IC FIFO 64X36X2 15NS 120QFP
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