OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

X9250US24Z-2.7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
1
®
X9250
Low Noise/Low Power/SPI Bus/256 Taps
Quad Digitally Controlled Potentiometers
(XDCP™)
FEATURES
• Four potentiometers in one package
• 256 resistor taps/pot - 0.4% resolution
• SPI serial interface
• Wiper resistance, 40Ω typical @ V
CC
= 5V
• Four nonvolatile data registers for each pot
• Nonvolatile storage of wiper position
• Standby current < 5µA max (total package)
• Power supplies
—V
CC
= 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• 100kΩ, 50kΩ total pot resistance
• High reliability
—Endurance – 100,000 data changes per bit per
register
—Register data retention - 100 years
• 24 Ld SOIC, 24 Ld TSSOP
• Dual supply version of X9251
• Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X9250 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array though the switches. Power up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
R
0
R
1
R
2
R
3
Wiper
Counter
Register
(WCR)
Resistor
Array
V
H1
/R
H1
V
L1
/R
L1
R
0
R
1
R
2
R
3
Wiper
Counter
Register
(WCR)
Interface
and
Control
Circuitry
CS
SCK
A0
A1
V
H0
/R
H0
V
L0
/R
L0
Data
8
V
W0
/R
W0
V
W1
/R
W1
SO
SI
R
0
R
1
R
2
R
3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
V
H2
/R
H2
V
L2
/R
L2
V
W2
/R
W2
R
0
R
1
R
2
R
3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 3
V
H3
/R
H3
V
L3
/R
H3
V
W3
/R
W3
Pot1
HOLD
WP
Pot 0
V
CC
V
SS
V+
V-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Data Sheet FN8165.3August 29, 2006
2
FN8165.3
August 29, 2006
Ordering Information
PART NUMBER
PART
MARKING V
CC
LIMITS (V)
POTENTIOMETER
ORGANIZATION (kΩ)
TEMP. RANGE
(°C) PACKAGE PKG. DWG. #
X9250TS24I X9250TS I 5 ±10% 100 -40 to +85 24 Ld SOIC (300 mil) M24.3
X9250TS24IZ (Note) X9250TS ZI -40 to +85 24 Ld SOIC (300 mil)
(Pb-free)
M24.3
X9250TV24I X9250TV I -40 to +85 24 Ld TSSOP
(4.4mm)
MDP0044
X9250TV24IZ (Note) X9250TV ZI -40 to +85 24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
X9250US24 X9250US 50 0 to +70 24 Ld SOIC (300 mil) M24.3
X9250US24Z (Note) X9250US Z 0 to +70 24 Ld SOIC (300 mil)
(Pb-free)
M24.3
X9250US24I X9250US I -40 to +85 24 Ld SOIC (300 mil) M24.3
X9250US24IZ (Note) X9250US ZI -40 to +85 24 Ld SOIC (300 mil)
(Pb-free)
M24.3
X9250UV24I X9250UV I -40 to +85 24 Ld TSSOP
(4.4mm)
MDP0044
X9250UV24IZ (Note) X9250UV ZI -40 to +85 24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
X9250TS24-2.7 X9250TS F -2.7 to 5.5 100 0 to +70 24 Ld SOIC (300 mil) M24.3
X9250TS24Z-2.7 (Note) X9250TS ZF 0 to +70 24 Ld SOIC (300 mil)
(Pb-free)
M24.3
X9250TS24I-2.7* X9250TS G -40 to +85 24 Ld SOIC (300 mil) M24.3
X9250TS24IZ-2.7*
(Note)
X9250TS ZG -40 to +85 24 Ld SOIC (300 mil)
(Pb-free)
M24.3
X9250TV24I-2.7 X9250TV G -40 to +85 24 Ld TSSOP
(4.4mm)
MDP0044
X9250TV24IZ-2.7 (Note) X9250TV ZG -40 to +85 24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
X9250US24-2.7* X9250US F 50 0 to +70 24 Ld SOIC (300 mil) M24.3
X9250US24Z-2.7* (Note) X9250US ZF 0 to +70 24 Ld SOIC (300 mil)
(Pb-free)
M24.3
X9250US24I-2.7 X9250US G -40 to +85 24 Ld SOIC (300 mil) M24.3
X9250US24IZ-2.7 (Note) X9250US ZG -40 to +85 24 Ld SOIC (300 mil)
(Pb-free)
M24.3
X9250UV24-2.7 X9250UV F 0 to +70 24 Ld TSSOP
(4.4mm)
MDP0044
X9250UV24Z-2.7 (Note) X9250UV ZF 0 to +70 24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
X9250UV24I-2.7 X9250UV G -40 to +85 24 Ld TSSOP
(4.4mm)
MDP0044
X9250UV24IZ-2.7 (Note) X9250UV ZG -40 to +85 24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
X9250
3
FN8165.3
August 29, 2006
PIN DESCRIPTIONS
Serial Output (SO)
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9250.
Chip Select (CS
)
When CS
is HIGH, the X9250 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS
LOW enables the X9250, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS
is
required prior to the start of any operation.
Hold (HOLD
)
HOLD
is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD
may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD
must
be brought LOW while SCK is LOW. To resume
communication, HOLD
is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
Device Address (A
0
- A
1
)
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9250. A maximum of 4 devices may occupy the
SPI serial bus.
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
- V
H3
/R
H3
), V
L
/R
L
(V
L0
/R
L0
-
V
L3
/R
L3
)
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer.
V
W
/R
W
(V
W0
/R
W0 -
V
W3
/R
W3
)
The wiper pins are equivalent to the wiper terminal of a
mechanical potentiometer.
Hardware Write Protect Input (WP
)
The WP
pin when LOW prevents nonvolatile writes to
the Data Registers.
Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
PIN NAMES
Symbol Description
SCK Serial Clock
SI, SO Serial Data
A
0
-A
1
Device Address
V
H0
/R
H0–
V
H3
/R
H3
,
V
L0
/R
L0–
V
L3
/R
L3
Potentiometer Pins
(terminal equivalent)
V
W0
/R
W0–
V
W3
/R
W3
Potentiometer Pins
(wiper equivalent)
WP
Hardware Write Protection
V+,V- Analog Supplies
V
CC
System Supply Voltage
V
SS
System Ground
NC No Connection
S0
A0
V
W3
/R
W3
V+
V
CC
V
L0
/R
L0
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
HOLD
SCK
V
L2
/R
L2
V
H2
/R
L2
V
W2
/R
W2
V–
V
SS
V
W1
/R
W1
V
H1
/R
H1
V
L1
/R
L1
SOIC/TSSOP
X9250
V
H3
/R
H3
14
13
11
12
V
L3
/R
L3
V
H0
/R
H0
V
W0
/R
W0
CS
A1
SI
WP
X9250
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

X9250US24Z-2.7

Mfr. #:
Buy X9250US24Z-2.7
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs SPI XDCP 100K QD 256 TAPS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet