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Microsemi Corporation
ZL30241 Data Sheet
3.2.1 Output Control Pins
The outputs are controlled by either a hardware OE pin or a OE register based on the value in the override bit in the
register. The default values of the override bits are zero, so the hardware pins controls the outputs. When the
hardware pin in enabled, the OEn SPI bit is read-only showing the current state of the realted hardware pin.
The OE1 and OE2 pins have 75 k pull-up resistors, while the OERef pin has a 50 k pull-down resistor.
To disable the hardware pin control, the associated override bit can be set in SPI register 0x2. When the ‘override’
bit is set to ‘1’, the external OE pin is ignored, and its value is no longer passed into register 0x2. Instead the value
of the OEn bit in register 0x2 is used in its place, and can be set through the SPI. Under this configuration, both the
override bit and OEn bit in register 0x2 must be set to ‘1’ to enable the output.
When an output changes from disabled to enabled, there is an approximately 2 microsecond delay before it begins
switching. During this delay, the outputs will settle to the appropriate DC levels according to the configured mode.
After this initial delay, the outputs will begin switching with precise periods and no ‘runt’ pulses.
When an output changes from enabled to disabled, it will stop switching at the appropriate DC levels according to
the configured mode. After it has stopped, the biases will be disabled and the output will be set to high impedance.
3.2.2 Output Electrical Format - (LVCMOS, LVDS, LVPECL, or HCSL)
The output format (mode) may be factory programmed and the output will operate in that mode at every power-up.
In addition, the mode may be changed by writing the new value into register 0x4 via the SPI. Although all three
output buffers are independent, the enables and modes may be programmed simultaneously.
Note that all of the output modes are differential except the LVCMOS mode. When LVCMOS is selected, the
positive output pin has the LVCMOS signal, and the negative (inverting) output pin is high impedance. In LVCMOS
mode, the output should be series terminated, or unterminated. Series termination consists of a 33 ohm resistor
placed within 0.25 inches of the ZL30241 package to absorb the reflections in the driven 50 ohm transmission line.
Differential output modes are highly recommended to preserve the high performance of the ZL30241, and also to
reduce noise pickup and generation.
3.3 Reference Input
Two input references are available for the PLL: a crystal oscillator which accepts fundamental crystals from 22 MHz
to 54 MHz and an external reference that may be supplied as a differential or single ended signal. Likewise, either
reference may be selected for an optional output buffer that supports LVCMOS, LVDS, LVPECL or HCSL.
Register 0x2 contains the reference select control bits. Register 0x3 contains the configuration bits for the input
reference buffer, prescaler, and reference output.
Three device pins are associated with the input signal: In_p, In_n and In_VCM. For differential signals, In_p and
In_n are the signal and In_VCM is the terminating voltage. A LVCMOS single ended signal needs to be applied to
In_p. The input signal is applied to a reference divider before being used by the PLL..
Note that the noise properties of the PLL reference matter a great deal to the output noise. At offset frequencies
below the PLL loop bandwidth, the PLL tracks and multiplies the reference phase noise. The crystal input offers a
very low phase noise reference, ensuring the output phase noise near the carrier is low. When selecting the input
reference, ensure the phase noise of the source is adequately low to meet the system noise requirements.
The reference divider is programmed via the refdiv[3:0] value in register 3; it divides by N+1 for a range of 1 to 16.
The In_p/In_n pins will accept LVCMOS, LVDS, LVPECL or HCSL signals. The register 0x3 bit 17, diff_ref_sel
must be set to 0 to select LVCMOS, and 1 for any differential signal. When LVCMOS is selected, it is applied to
REFIN (pin 42). When a LVCMOS signal is used, it must be applied to In_p.
