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ZL30241LDG1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
List of Tables
ZL30241 Data Sheet
4
Microsemi Corporation
Table 1 - Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2 - Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3 - Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5 - Xtal_gain[3:0] Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4 - Reference Input (In_p/In_n) Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6 - Interpretation of S Parameter in Ratio Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7 - SPI Operation Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8 - Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9 - Thermal Care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
ZL30241 Data Sheet
5
Microsemi Corporation
1.0 Pin Diagram
2.0 Pin Description
Pin Name
48
QFN
Pin #
Name Type Description
In_p
In_n
42
41
Input INPUT
Selectable
Input (singled ended or differential).
Can be selected as the reference clock for
PLL1, and/or the Reference Clock Output.
When not used for a single ended crystal
oscillator, it can be differential with a DC bias
provided by the In_VCM pin.
In_VCM 40 Input Bias DC When In_p/In_n act as a differential input, this
pin connects to the midpoint of the two 50 ohm
internal termination resistors.
XO1
XO2
39
38
Crystal Input 1 INPUT External Crystal should be connected to these
pins to drive the internal oscillator reference.
This input can be used as the reference for
PLL1 and/or the Reference Clock Output.
OUT1_p
OUT1_n
2
3
Clock Output 1 OUTPUT
Selectable
1
Clock Output derived from PLL1. Supports
frequencies up to the device maximum. When
used in LVCMOS mode, OUT1_p is the active
pin and OUT1_n is not used and is High-Z.
Table 1 - Pin Description
RefOut_p
NC
NC
VDD
VDDA6
In_p
In_n
In_VCM
XO1
XO2
NC
NC
NC
NC
VDDA4
NC
NC
NC
NC
PD1_b
VDDA3
FILTER1+
FILTER1-
OE1
OE2
SDO
NC
NC
NC
SDI
SCK
CSB\PROG RefOut_n
VSSO1
OUT1_p
OUT1_n
VDDO1
VDDA1
VDDO2
OUT2_p
OUT2_n
VSSO2
VSS
OEREF
43
48
47
46
45
44
42
41
40
39
38
1
2
3
4
5
6
7
8
9
10
35
34
33
32
31
30
29
28
27
26
18
13
14
15
16
17
19
20
21
22
23
11
25
VDDA2
12
NC
24
VSS
36
VDDA5
37
48 Pin QFN
(Top View)
7mm x 7mm Package
Pin Pitch 0.5mm
ZL30241 Data Sheet
6
Microsemi Corporation
OE1 15 Output Enable 1 INPUT
LVCMOS
Output Enable for Clock Output 1. Active High,
When the output is disabled, it places OUT1_p
& OUT1_n into High-Z state.
This pin is internally pulled-up to VDD through
75 kohms.
OUT2_p
OUT2_n
7
8
Clock Output 2 OUTPUT
Selectable
1
Clock Output derived from PLL1. Supports
frequencies up to the device maximum. When
used in LVCMOS mode, OUT2_p is the active
pin. OUT2_n is not used and is High-Z.
OE2 16 Output Enable 2 INPUT
LVCMOS
Output Enable for Clock Output 2. Active High,
When the output is disabled, it places OUT2_p
& OUT2_n into High-Z state.
This pin is internally pulled-up to VDD through
75 kohms.
RefOut_p
RefOut_n
44
43
Reference
Output
OUTPUT
Selectable
1
Reference Clock Output. Provides a copy of the
Reference Input (or Crystal input) frequency.
OEREF 11 Output Enable for
REFOUT
INPUT
LVCMOS
Output Enable for Reference Output. Active
High.
When the output is disabled, it places RefOut_p
& RefOut_n into High-Z state.
This pin is internally pulled-up to VDD through
50 kohms.
SCK 19 Serial Clock INPUT
LVCMOS
Clock Input for SPI control.
SDI 20 Serial Data In INPUT
LVCMOS
Data Input for SPI control.
SDO 17 Serial Data Out OUTPUT
LVCMOS
Data Output for SPI control.
CSB 18 Chip Select INPUT
LVCMOS
Chip Select for SPI control.
This pin also functions as a programming pin for
the internal fuses. If this pin is held above 3.3 V,
then the device will accept SPI commands to
program internal fuses.
This pin is internally pulled-up to VDD through
75 kohms.
FILTER1+
FILTER1-
13
14
PLL1 Filter Analog CP external Filter capacitor input and return for
PLL1
PD1_b 26 Power Down 1
(Inverted)
INPUT
LVCMOS
Active Low Power Down pin for PLL1. When
active, PLL1 enters power down state; all
outputs from PLL1 are disabled, High-Z.
This pin is internally pulled-down to VSS
through 50 kohms.
Pin Name
48
QFN
Pin #
Name Type Description
Table 1 - Pin Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

ZL30241LDG1

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Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Prec Univ Clock Gen and NCO
Lifecycle:
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