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Microsemi Corporation
ZL30241 Data Sheet
As a special case, for frequencies between 750 MHz and 778 MHz which cannot be accessed with divider of 4 or 5,
a divider of 4.5 is provided. To divide by 4.5, set the outn_4p5. When this bit is set, the associated output divider will
ignore the value in register 5 and divide by 4.5.
In any case that the change to the feedback divider is small, i.e., a change in phase or a few ppm in frequency, the
output frequencies will change smoothly with no sudden phase step. The change in the feedback divider will be
instantaneous, but the VCO response will be smoothed by the loop filter. Thus any changes small enough not to
cause lock disturbance will be smooth and continuous.
3.7 Status Indicators
The lock status of the PLL may be monitored via the pllx_lock bit in register 15, bit 21. A value of "1" indicates lock,
and is the normal condition. A 0 indicates out of lock, or the absence of a reference (either input signal or crystal).
3.8 Resets
The ZL30241 does not need a reset after power is applied, but some other configuration changes require a reset of
the associated subsystem in the device. If the feedback divisor (fbdiv), M, or S value is changed in a PLL, then the
corresponding fbdiv_resetn (register 0x7 bit 14) bit needs to be toggled. If the output divisor (register 0x5) value is
changed, output1_2_reset (register 0x7, bit 13) needs to be toggled.
4.0 SPI Programming
At power up, the ZL30241 takes on the values programmed by the factory. Thereafter, the SPI may be used to
overwrite any value. Care should be taken not to overwrite the factory-programmed calibrations (registers 10
through 14). The maximum SPI clock rate is 10 MHz. All transfers are multiples of 8-bit bytes, and are read and
written with most significant byte first, and most significant bit first.
Serial Peripheral Interface Description
1. SCK is the clock input to the SPI interface.
2. SDI is the data input to the SPI interface. Data must be valid by the rising edge of SCK.
3. SDO is the data output from the SPI interface. Data at SDO will be valid 12 ns after the rising edge of the clock.
4. CSB is the active-low enable signal for the SPI. The rising edge of CSB disables the SPI controller on the slave
device. In the disabled state, the SPI controller will not respond to events on SCK or SDI, and SDO is in a high-
impedance state. The falling edge of CSB enables the SPI for read/write access, and resets it to the initial state
(awaiting the control/address byte). Register contents are not reset or otherwise altered by cycling CSB.
5. Multiple SPI slave devices may communicate with the same SPI master by sharing SDO, SDI, and SCK, and
addressing each device with its individual CSB signal.
6. Upon power-up, all SPI read/write register contents are set to default values. For those registers associated with
fuse addresses, the state of the fuse determines the default value.
7. The SPI master initiates a data transfer by dropping CSB to enable the slave device, followed by eight bits of
data applied synchronously with eight pulses of SCK. The first four bits define the opcode, and the last four bits
define the register to be addressed. The data stream is shown in the following diagram:
