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Microsemi Corporation
ZL30241 Data Sheet
3.0 Description
The ZL30241 is a single PLL clock generator with two programmable outputs. The PLL with either a crystal, crystal
oscillator or external reference input frequency, produce up to two related output frequencies. Each output can
select between LVCMOS, LVDS, LVPECL, and HCSL. The input crystal is a low cost fundamental mode type, and
the ZL30241 provides programmable gain and load capacitors for the crystal inputs. Alternatively, a multi-standard
input reference can be used with a dedicated divider. The crystal or external reference is also available as an output
bypassing the PLL for test purposes.
For the PLL, three modes of operation can be selected: integer mode, fractional mode, and ratio mode. The integer
mode provides lowest noise and behaves like a conventional PLL with whole number dividers. The device will get
interger mode performance even with 3 fractional bits in use allowing eights in the feedback divider without
increasing the jitter.
The fractional mode allows the feedback divider to have an 8 bit integer part and 28 bit fractional part, resulting in a
frequency resolution of 0.1 ppb or better. Finally, the ratio mode offers frequency translation of an N + X/Y nature,
ideal for frequency translation applications like SONET and OTN.
The PLL has a VCO that operates between 3053 MHz and 3677 MHz. There are two output dividers on the PLL,
with a range of 4 to 259. In order to prevent a “frequency hole” between 750.6 MHz and 777.5 MHz, a special
divide by 4.5 mode is also included. Any output frequency between 12 MHz and 914 MHz can be produced on the
differential output.
Additional features include loss of lock indicators and high speed SPI control. The ZL30241 has factory
programmed defaults and may also be configured through the SPI port.
3.1 Input Configuration
The In_p/In_n pins can take one of four modes.
Table 2 - Input modes
Refmode [1:0] Mode
00 LVCMOS
01 LVDS
10 LVPECL
11 HCSL
