ZL30241LDG1 Datasheet ZL30241LDF1, ZL30241LDG1 | P16-P18

Microsemi Corporation

ZL30241 Data Sheet

Figure 8 - Example SPI Read

The register addresses ADDR[3:0] define an address space for up to 16 registers. The opcode OP[3:0] is not fully

utilized in this implementation. The following four opcodes are defined by the interface:

The default state for CSB high is opcode zero, or no-op. The “read” opcodes are followed by one or more series of

eight SCK pulses. Data from the register addressed by ADDR are placed on SDO, msb first. The number of eight-

pulse cycles is determined by the type of register defined at address ADDR. The “write” opcodes are followed by

one or more series of eight SCK pulses, with data to be written to the addressed register placed on SDI and valid at

the rising edge of SCK.

The core circuits of the chip see the new contents of each byte on the falling edge of the eighth SCK pulse, with the

exception of registers 6 and 8, all bits of which are updated simultaneously on the falling edge of the eighth SCK

pulse of the last (5th) byte.

Figure 9 - Read (opcode 2) cycle

OP[3:0] Operation

0000 no-op

0001 write data

0010 read data

0011 reserved

Table 7 - SPI Operation Codes

OP[3] OP[2] OP[1] OP[0] ADDR[3] ADDR[2] ADDR[1] ADDR[0]

CSB

SCK

SDI

SDO

SDO output is defined to be zero during the command and address input cycles

data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0]

SDO data valid

any data on SDI are ignored

CSB

SCK

SDI

SDO

CSB must be held low through the entire operation

Microsemi Corporation

ZL30241 Data Sheet

Figure 10 - Write (opcode 1) cycle

data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0]

SDO output is defined to be zero during the data input cycle

CSB

SCK

SDI

SDO

CSB must be held low through the entire operation

ZL30241 Data Sheet

Microsemi Corporation

5.0 Register Map

The device is controlled by accessing registers through the SPI interface.

Reg_Addr

(Hex)

Size

(Bytes)

Name

Default Value

(Hex)

Description Type

Miscellaneous Registers

0x0 4 Chip_id 0x13100000 Chip Identification R

0x1 6 Product_id 0x7AF000000000 Product Identification R

0x2 3 Device_Config1 0x00AA0A External pin read back and

override

R/W

0x3 4 Device_Config2 0x100F0000 Reference buffer/divider,

interpolated value increment,

and miscellaneous

R/W

0x4 2 Buffer_config 0x0000 Input and output buffer

configuration

R/W

0x5 4 Output_divider 0x00000000 Control the value of the output

dividers

R/W

0x6 5 PLL1_config1 0x000000000E Control the value of the feed-

back divider in PLL1

R/W

0x7 5 PLL1_config2 0x0000000000 Control PLL1 parameters R/W

0x8 5 Reserved - Reserved -

0x9 5 Reserved - Reserved -

0xA 2 Reserved - Reserved -

0xB 4 Reserved - Reserved -

0xC 4 PLL1 band 0x00000000 Control the PLL1 band R/W

0xD 4 Reserved - Reserved -

0xE 4 Reserved - Reserved -

0xF 3 PLL_lock 0x060000 Determine if either PLL is

locked

Table 8 - Register Map

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P40

ZL30241LDG1

Mfr. #:

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