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ZL30241LDG1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
ZL30241 Data Sheet
25
Microsemi Corporation
28:24 fsel1[4:0] VCO frequency band selection
Selection:
Value minimum nominal maximum
0 3642 3654 3677
1 3615 3623 3642
2 3583 3597 3615
3 3556 3568 3583
4 3532 3542 3556
5 3509 3518 3532
6 3486 3496 3509
7 3463 3473 3486
8 3440 3450 3463
9 3416 3426 3440
10 3391 3402 3416
11 3375 3382 3391
12 3360 3366 3375
13 3345 3350 3360
14 3307 3322 3345
15 3290 3298 3307
16 3268 3278 3290
17 3249 3256 3268
18 3228 3237 3249
19 3209 3217 3228
20 3189 3198 3209
21 3171 3179 3189
22 3154 3161 3171
23 3135 3143 3154
24 3119 3126 3135
25 3100 3108 3119
26 3084 3091 3100
27 3053 3072 3084
Note: For fsel1 of 0 to 13, KVCO must be set to 0. For fsel1 values of 14- 27, KVCO
must be set to 1. Fsel1 can be found in register 0xC.
23 Reserved Leave as default
22:21 S1[1:0] See description for PLL1_configure_1 bits 39:4
20:16 Reserved Leave as default
15 advance1 Reserved
14 fbdiv_reset1 Toggle this bit to 1 after a change in M1 or divval1
13 output1_2_reset Toggle this bit to 1 to reset the outputs on PLL1
Register_Address: 0x7
Register Name: PLL1_config2
Default Value: 0x0000000000
Type: R/W
Bit Field Function Name Description
ZL30241 Data Sheet
26
Microsemi Corporation
12 force_reset1 Toggle this bit to 1 to reset PLL1
This signal forces a reset cycle that generates synchronization pulses for
the outputs of PLL1.
11 decline1 Reserved
10 rational_mode1 See description for PLL1_configure_1 bits 39:4
9:0 modulus1[15:6] See description for PLL1_configure_1 bits 39:4
Register_Address: 0x8
Register Name: Reserved
Default Value: 0x0000000000
Type: R
Bit Field Function Name Description
39:4 Reserved Leave as default
3:0 Reserved Leave as default
Register_Address: 0x9
Register Name: Reserved
Default Value: 0x0000000000
Type: R
Bit Field Function Name Description
39:37 Reserved Leave as default
36:32 Reserved Leave as default
31:29 Reserved Leave as default
28:24 Reserved Leave as default
23 Reserved Leave as default
22:21 Reserved Leave as default
20:16 Reserved Leave as default
15 Reserved Leave as default
Register_Address: 0x7
Register Name: PLL1_config2
Default Value: 0x0000000000
Type: R/W
Bit Field Function Name Description
ZL30241 Data Sheet
27
Microsemi Corporation
14 Reserved Leave as default
13 Reserved Leave as default
12 Reserved Leave as default
11 Reserved Leave as default
10 Reserved Leave as default
9:0 Reserved Leave as default
Register_Address: 0xA
Register Name: Reserved
Default Value: -
Type: R
Bit Field Function Name Description
15 Reserved Leave as default
14:12 Reserved Leave as default
11:9 Reserved Leave as default
8 Reserved Leave as default
7:0 Reserved Leave as default
Register_Address: 0xB
Register Name: Reserved
Default Value: -
Type: R
Bit Field Function Name Description
31:0 Reserved Leave as default
Register_Address: 0x9
Register Name: Reserved
Default Value: 0x0000000000
Type: R
Bit Field Function Name Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

ZL30241LDG1

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Buy ZL30241LDG1
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Prec Univ Clock Gen and NCO
Lifecycle:
New from this manufacturer.
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