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SC68C652BIB48,128

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43
SC68C652B_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 2 November 2009 10 of 43
NXP Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
6.4 Hardware flow control
When automatic hardware flow control is enabled, the SC68C652B monitors the CTSn pin
for a remote buffer overflow indication and controls the RTSn pin for local buffer overflows.
Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to
a logic 1. If CTSn transitions from a logic 0 to a logic 1 indicating a flow control request,
ISR[5] will be set to a logic 1 (if enabled via IER[6:7]), and the SC68C652B will suspend
TXn transmissions as soon as the stop bit of the character in process is shifted out.
Transmission is resumed after the CTSn input returns to a logic 0, indicating more data
may be sent.
With the auto-RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTSn pin will not be forced to a logic 1 (RTS
off), until the receive FIFO reaches the next trigger level. However, the RTSn pin will return
to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the
programmed trigger level. However, under the above described conditions, the
SC68C652B will continue to accept data until the receive FIFO is full.
6.5 Software flow control
When software flow control is enabled, the SC68C652B compares one or two sequential
receive data characters with the programmed Xon or Xoff character value(s). If received
character(s) match the programmed Xoff values, the SC68C652B will halt transmission
as soon as the current character(s) has completed transmission. When a match occurs,
the receive ready (if enabled via Xoff IER[5]) flags will be set and the interrupt output pin
(if receive interrupt is enabled) will be activated. Following a suspension due to a match of
the Xoff characters’ values, the SC68C652B will monitor the receive data stream for a
match to the Xon1/Xon2 character value(s). If a match is found, the SC68C652B will
resume operation and clear the flags (ISR[4]).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow control.
Different conditions can be set to detect Xon/Xoff characters and suspend/resume
transmissions. When double 8-bit Xon/Xoff characters are selected, the SC68C652B
compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TXn transmissions accordingly. Under the above
described flow control mechanisms, flow control characters are not placed (stacked) in the
user accessible receive data buffer or FIFO. When using a software flow control, the
Xon/Xoff characters cannot be used for data transfer.
In the event that the receive buffer is overfilling and flow control needs to be executed, the
SC68C652B automatically sends an Xoff message (when enabled) via the serial TXn
output to the remote modem. The SC68C652B sends the Xoff1/Xoff2 characters as soon
Table 5. Flow control mechanism
Selected trigger level
(characters)
IRQ pin activation Negate RTS or
send Xoff
Assert RTS or
send Xon
RX TX
881680
16 16 8 16 7
24 24 24 24 15
28 28 30 28 23
SC68C652B_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 2 November 2009 11 of 43
NXP Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
as received data passes the programmed trigger level. To clear this condition, the
SC68C652B will transmit the programmed Xon1/Xon2 characters as soon as receive data
drops below the programmed trigger level.
6.6 Special feature software flow control
A special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit
character is detected, wit will be placed on the user-accessible data stack along with
normal incoming receive data. This condition is selected in conjunction with EFR[3:0].
Note that software flow control should be turned off when using this special mode by
setting EFR[3:0] to a logic 0.
The SC68C652B compares each incoming receive character with Xoff2 data. If a match
exists, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate
detection of a special character. Although Table 9 “SC68C652B internal registers” shows
each X-register with eight bits of character information, the actual number of bits is
dependent on the programmed word length. Line Control Register bits LCR[1:0] define the
number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length
selected by LCR[1:0] also determine the number of bits that will be used for the special
character comparison. Bit 0 in the X-registers corresponds with the LSB bit for the receive
character.
6.7 Hardware/software and time-out interrupts
The interrupts are enabled by IER[3:0]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC68C652B
will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to
continuing operations. The ISR register provides the current singular highest priority
interrupt only. It could be noted that CTS and RTS interrupts have lowest interrupt priority.
A condition can exist where a higher priority interrupt may mask the lower priority
CTS/RTS interrupt(s). Only after servicing the higher pending interrupt will the lower
priority CTS/RTS interrupt(s) be reflected in the status register. Servicing the interrupt
without investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the SC68C652B
FIFO may hold more characters than the programmed trigger level. Following the removal
of a data byte, the user should re-check LSR[0] for additional characters. A Receive
Time-Out will not occur if the receive FIFO is empty. The time-out counter is reset at the
center of each stop bit received or each time the receive holding register (RHR) is read.
The actual time-out value is 4 character time, including data information length, start bit,
parity bit, and the size of stop bit, that is, 1×, 1.5×, or 2× bit times.
SC68C652B_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 2 November 2009 12 of 43
NXP Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
6.8 Programmable baud rate generator
The SC68C652B supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s modem
that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s
ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s.
The SC68C652B can support a standard data rate of 921.6 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent transmit/receive channel control. The programmable baud rate generator is
capable of operating with a frequency of up to 80 MHz. To obtain maximum data rate, it is
necessary to use full rail swing on the clock input. The SC68C652B can be configured for
internal or external clock operation. For internal clock oscillator operation, an industry
standard microprocessor crystal is connected externally between the XTAL1 and XTAL2
pins. Alternatively, an external clock can be connected to the XTAL1 pin to clock the
internal baud rate generator for standard or custom rates (see Table 6).
The generator divides the input 16× clock by any divisor from 1 to (2
16
− 1). The
SC68C652B divides the basic external clock by 16. The basic 16× clock provides table
rates to support standard and custom applications using the same system design. The
rate table is configured via the DLL and DLM internal register functions. Customized baud
rates can be achieved by selecting the proper divisor values for the MSB and LSB
sections of baud rate generator.
Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a
user capability for selecting the desired final baud rate. The example in Table 6 shows the
selectable baud rate table available when using a 1.8432 MHz external clock input.
Fig 3. Crystal oscillator connection
002aab325
C2
33 pF
XTAL1 XTAL2
X1
1.8432 MHz
C1
22 pF
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SC68C652BIB48,128

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NXP Semiconductors
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IC UART DUAL 48LQFP
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