SC68C652B_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 2 November 2009 30 of 43
NXP Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
10. Dynamic characteristics
[1] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
[2] Applies to external clock; crystal oscillator max 24 MHz.
[3]
[4] Reset pulse must happen when CS is inactive.
Table 29. Dynamic characteristics
T
amb
=
−
40
°
C to +85
°
C; tolerance of V
CC
±
10 %, unless specified otherwise.
Symbol Parameter Conditions V
CC
= 2.5 V V
CC
= 3.3 V and 5 V Unit
Min Max Min Max
t
d1
R/W to chip select 10 - 10 - ns
t
d2
read cycle delay 25 pF load 20 - 20 - ns
t
d3
delay from CS to data 25 pF load - 77 - 26 ns
t
d4
data disable time 25 pF load - 15 - 15 ns
t
d6
write cycle delay 25 - 25 - ns
t
d7
delay from write to output 25 pF load - 100 - 33 ns
t
d8
delay to set interrupt from modem
input
25 pF load - 100 - 24 ns
t
d9
delay to reset interrupt from read 25 pF load - 100 - 24 ns
t
d10
delay from stop to set interrupt - 1T
RCLK
[1]
-1T
RCLK
[1]
ns
t
d11
delay from read to reset interrupt 25 pF load - 100 - 29 ns
t
d12
delay from start to set interrupt - 100 - 100 ns
t
d13
delay from write to transmit start 8T
RCLK
[1]
24T
RCLK
[1]
8T
RCLK
[1]
24T
RCLK
[1]
ns
t
d14
delay from write to reset interrupt - 100 - 70 ns
t
d15
delay from stop to set RXRDY-1T
RCLK
[1]
-1T
RCLK
[1]
ns
t
d16
delay from read to reset RXRDY - 100 - 75 ns
t
d17
delay from write to set TXRDY - 100 - 70 ns
t
d18
delay from start to reset TXRDY - 16T
RCLK
[1]
- 16T
RCLK
[1]
ns
t
h2
R/W hold time from CS 10 - 10 - ns
t
h3
data hold time 15 - 15 - ns
t
h4
address hold time 15 - 15 - ns
t
WH
pulse width HIGH 10 - 6 - ns
t
WL
pulse width LOW 10 - 6 - ns
f
XTAL
clock speed
[2][3]
- 48 - 80 MHz
t
(RESET)
RESET pulse width
[4]
200 - 200 - ns
t
su1
address set-up time 10 - 10 - ns
t
su2
data set-up time 16 - 16 - ns
t
w1
CS strobe width 77 - 30 - ns
f
XTAL
1
t
wclk()
---------------
=
