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SC68C652BIB48,128

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43
SC68C652B_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 2 November 2009 25 of 43
NXP Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the modem, or
other peripheral device to which the SC68C652B is connected. Four bits of this register
are used to indicate the changed information. These bits are set to a logic 1 whenever a
control input from the modem changes state. These bits are set to a logic 0 whenever the
CPU reads this register.
[1] Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.
7.9 Scratchpad Register (SPR)
The SC68C652B provides a temporary data register to store 8 bits of user information.
Table 22. Modem Status Register bits description
Bit Symbol Description
7 MSR[7] CD. During normal operation, this bit is the complement of the
CDn input pin.
Reading this bit in the loopback mode produces the state of MCR[3] (
OP2).
6 MSR[6] RI. During normal operation, this bit is the complement of the
RIn input pin.
Reading this bit in the loopback mode produces the state of MCR[2] (
OP1).
5 MSR[5] DSR. During normal operation, this bit is the complement of the
DSRn input
pin. During the loopback mode, this bit is equivalent to the state of MCR[0].
4 MSR[4] CTS. During normal operation, this bit is the complement of the
CTSn input
pin. During the loopback mode, this bit is equivalent to the state of MCR[1].
3 MSR[3] ∆
CD
[1]
logic 0 = no change of state on CDn pin (normal default condition)
logic 1 = the
CDn input pin to the SC68C652B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
2 MSR[2] ∆
RI
[1]
logic 0 = no change of state on RIn pin (normal default condition)
logic 1 = the
RIn input pin to the SC68C652B has changed from a logic 0
to a logic 1. A modem Status Interrupt will be generated.
1 MSR[1] ∆
DSR
[1]
logic 0 = no change of state on DSRn pin (normal default condition)
logic 1 = the
DSRn input pin to the SC68C652B has changed state since
the last time it was read. A modem Status Interrupt will be generated.
0 MSR[0] ∆
CTS
[1]
logic 0 = no change of state on CTSn pin (normal default condition)
logic 1 = the
CTSn input pin to the SC68C652B has changed state since
the last time it was read. A modem Status Interrupt will be generated.
SC68C652B_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 2 November 2009 26 of 43
NXP Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
7.10 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
Bits 0 through 4 provide single or dual character software flow control selection. When the
Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are
concatenated into two sequential numbers.
Table 23. Enhanced Feature Register bits description
Bit Symbol Description
7 EFR[7] Automatic CTS flow control
logic 0 = automatic CTS flow control is disabled (normal default condition)
logic 1 = enable automatic CTS flow control. Transmission will stop when
CTSn goes to a logic 1. Transmission will resume when the CTSn pin returns
to a logic 0.
6 EFR[6] Automatic RTS flow control. Automatic RTS may be used for hardware flow
control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will be
generated when the receive FIFO is filled to the programmed trigger level and
RTSn will go to a logic 1 at the next trigger level. RTSn will return to a logic 0
when data is unloaded below the next lower trigger level (programmed trigger
level 1). The state of this register bit changes with the status of the hardware
flow control.
RTSn functions normally when hardware flow control is disabled.
logic 0 = automatic RTS flow control is disabled (normal default condition)
logic 1 = enable automatic RTS flow control.
5 EFR[5] Special character detect
logic 0 = Special character detect disabled (normal default condition)
logic 1 = Special character detect enabled. The SC68C652B compares each
incoming receive character with Xoff2 data. If a match exists, the received
data will be transferred to FIFO and ISR[4] will be set to indicate detection of
special character. Bit-0 in the X-registers corresponds with the LSB bit for the
receive character. When this feature is enabled, the normal software flow
control must be disabled (EFR[3:0] must be set to a logic 0).
4 EFR[4] Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4], and
MCR[7:5] can be modified and latched. After modifying any bits in the enhanced
registers, EFR[4] can be set to a logic 0 to latch the new values. This feature
prevents existing software from altering or overwriting the SC68C652B
enhanced functions.
logic 0 = disable/latch enhanced features. IER[7:4], ISR[5:4], FCR[5:4], and
MCR[7:5] are saved to retain the user settings, then IER[7:4] ISR[5:4],
FCR[5:4], and MCR[7:5] are set to a logic 0 to be compatible with SC16C554
mode. (Normal default condition.)
logic 1 = enables the enhanced functions. When this bit is set to a logic 1, all
enhanced features of the SC68C652B are enabled and user settings stored
during a reset will be restored.
3:0 EFR[3:0] Cont-3:0 TX, RX control. Logic 0 or cleared is the default condition.
Combinations of software flow control can be selected by programming these
bits. See
Table 24.
SC68C652B_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 2 November 2009 27 of 43
NXP Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
[1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer.
7.11 SC68C652B external reset condition
Table 24. Software flow control functions
[1]
Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software flow controls
0 0 X X no transmit flow control
1 0 X X transmit Xon1/Xoff1
0 1 X X transmit Xon2/Xoff2
1 1 X X transmit Xon1 and Xon2/Xoff1 and Xoff2
X X 0 0 no receive flow control
X X 1 0 receiver compares Xon1/Xoff1
X X 0 1 receiver compares Xon2/Xoff2
1011transmit Xon1/Xoff1
receiver compares Xon1 and Xon2/Xoff1 and Xoff2
0111transmit Xon2/Xoff2
receiver compares Xon1 and Xon2/Xoff1 and Xoff2
1111transmit Xon1 and Xon2/Xoff1 and Xoff2
receiver compares Xon1 and Xon2/Xoff1 and Xoff2
Table 25. Reset state for registers
Register Reset state
IER IER[7:0] = 0
FCR FCR[7:0] = 0
ISR ISR[7:1] = 0; ISR[0] = 1
LCR LCR[7:0] = 0
MCR MCR[7:0] = 0
LSR LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0
MSR MSR[7:4] = input signals; MSR[3:0] = 0
SPR SFR[7:0] = 1
DLL DLL[7:0] = X
DLM DLM[7:0] = X
Table 26. Reset state for outputs
Output Reset state
TXA, TXB logic 1
OP2A, OP2B logic 1
RTSA, RTSB logic 1
DTRA, DTRB logic 1
IRQ 3-state condition
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SC68C652BIB48,128

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NXP Semiconductors
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IC UART DUAL 48LQFP
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