SC68C652B_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 2 November 2009 13 of 43
NXP Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
6.9 DMA operation
The SC68C652B FIFO trigger level provides additional flexibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in the
DMA mode (FCR[3]). The DMA mode affects the state of the RXRDYn and TXRDYn
output pins. Table 7 and Table 8 show this.
6.10 Loopback mode
The internal loopback capability allows on-board diagnostics. In the loopback mode, the
normal modem interface pins are disconnected and reconfigured for loopback internally
(see Figure 4). MCR[3:0] register bits are used for controlling loopback diagnostic testing.
In the loopback mode, the transmitter output pin (TXn) and the receiver input pin (RXn)
are disconnected from their associated interface pins, and instead are connected together
internally. The CTSn, DSRn, CDn, and RIn pins are disconnected from their normal
modem control inputs pins, and instead are connected internally to MCR[1] RTS,
Table 6. Baud rate generator programming table using a 1.8432 MHz clock
Output
baud rate
Output
16× clock divisor
(decimal)
Output
16× clock divisor
(HEX)
DLM
program value
(HEX)
DLL
program value
(HEX)
50 2304 900 09 00
75 1536 600 06 00
110 1047 417 04 17
150 768 300 03 00
300 384 180 01 80
600 192 C0 00 C0
1200 96 60 00 60
2400 48 30 00 30
3600 32 20 00 20
4800 24 18 00 18
7200 16 10 00 10
9600 12 0C 00 0C
19.2 k 6 06 00 06
38.4 k 3 03 00 03
57.6 k 2 02 00 02
115.2 k 1 01 00 01
Table 7. Effect of DMA mode on state of RXRDYn pin
Non-DMA mode DMA mode
1 = FIFO empty 0-to-1 transition when FIFO empties
0 = at least 1 byte in FIFO 1-to-0 transition when FIFO reaches trigger level,
or time-out occurs
Table 8. Effect of DMA mode on state of
TXRDYn pin
Non-DMA mode DMA mode
1 = at least 1 byte in FIFO 0-to-1 transition when FIFO becomes full
0 = FIFO empty 1-to-0 transition when FIFO goes below trigger level
