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SC68C652BIB48,128

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SC68C652B_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 2 November 2009 16 of 43
NXP Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D[7:0]) to the
TSR and UART via the THR, providing that the THR is empty. The THR empty flag in the
LSR register will be set to a logic 1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can be performed when the THR
empty flag is set (logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR empty).
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a
Receive Serial Shift Register (RSR). Receive data is removed from the SC68C652B and
receive FIFO by reading the RHR register. The receive section provides a mechanism to
prevent false starts. On the falling edge of a start or false start bit, an internal receiver
counter starts counting clocks at the 16× clock rate. After 7
1
⁄
2
clocks, the start bit time
should be shifted to the center of the start bit. At this time the start bit is sampled, and if it
is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver
from assembling a false character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the IRQ output pin.
Table 10. Interrupt Enable Register bits description
Bit Symbol Description
7 IER[7] CTS interrupt
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt. The SC68C652B issues an interrupt
when the
CTSn pin transitions from a logic 0 to a logic 1.
6 IER[6] RTS interrupt
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt. The SC68C652B issues an interrupt
when the
RTSn pin transitions from a logic 0 to a logic 1.
5 IER[5] Xoff interrupt
logic 0 = disable the software flow control, receive Xoff interrupt (normal
default condition)
logic 1 = enable the software flow control, receive Xoff interrupt
4 IER[4] Sleep mode
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode
3 IER[3] Modem Status Interrupt. This interrupt will be issued whenever there is a
modem status change as reflected in MSR[3:0].
logic 0 = disable the modem status register interrupt (normal default
condition)
logic 1 = enable the modem status register interrupt
SC68C652B_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 2 November 2009 17 of 43
NXP Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation
When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are
enabled, the receive interrupts and register status will reflect the following:
• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU
when the receive FIFO has reached the programmed trigger level. It will be cleared
when the receive FIFO drops below the programmed trigger level.
• Receive FIFO status will also be reflected in the user accessible ISR register when
the receive FIFO trigger level is reached. Both the ISR register receive status bit and
the interrupt will be cleared when the FIFO drops below the trigger level.
• The receive data ready bit (LSR[0]) is set as soon as a character is transferred from
the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.
• When the Transmit FIFO and interrupts are enabled, an interrupt is generated when
the transmit FIFO is empty due to the unloading of the data by the TSR and UART for
transmission via the transmission media. The interrupt is cleared either by reading the
ISR register, or by loading the THR with new data characters.
2 IER[2] Receive Line Status interrupt. This interrupt will be issued whenever a
receive data error condition exists as reflected in LSR[4:1].
logic 0 = disable the receiver line status interrupt (normal default
condition)
logic 1 = enable the receiver line status interrupt
1 IER[1] Transmit Holding Register interrupt. In the 16C450 mode, this interrupt will
be issued whenever the THR is empty, and is associated with LSR[5]. In
the FIFO modes, this interrupt will be issued whenever the FIFO is empty.
logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt
(normal default condition)
logic 1 = enable the TXRDY (ISR level 3) interrupt
0 IER[0] Receive Holding Register. In the 16C450 mode, this interrupt will be
issued when the RHR has data, or is cleared when the RHR is empty. In
the FIFO mode, this interrupt will be issued when the FIFO has reached
the programmed trigger level or is cleared when the FIFO drops below the
trigger level.
logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt
(normal default condition)
logic 1 = enable the RXRDY (ISR level 2) interrupt
Table 10. Interrupt Enable Register bits description
…continued
Bit Symbol Description
SC68C652B_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 2 November 2009 18 of 43
NXP Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
7.2.2 IER versus Receive/Transmit FIFO polled mode operation
When FCR[0] = logic 1, resetting IER[0:3] enables the SC68C652B in the FIFO polled
mode of operation. In this mode, interrupts are not generated and the user must poll the
LSR register for transmit and/or receive data status. Since the receiver and transmitter
have separate bits in the LSR either or both can be used in the polled mode by selecting
respective transmit or receive control bit(s).
• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
• LSR[4:1] will provide the type of receive errors, or a receive break, if encountered.
• LSR[5] will indicate when the transmit FIFO is empty.
• LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.
• LSR[7] will show if any FIFO data errors occurred.
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels, and select the DMA mode.
7.3.1 DMA mode
7.3.1.1 Mode 0 (FCR bit 3 = 0)
Set and enable the interrupt for each single transmit or receive operation, and is similar to
the 16C450 mode. Transmit Ready pin (TXRDYn) will go to a logic 0 whenever the FIFO
(THR, if FIFO is not enabled) is empty. Receive Ready pin (RXRDYn) will go to a logic 0
whenever the Receive Holding Register (RHR) is loaded with a character.
7.3.1.2 Mode 1 (FCR bit 3 = 1)
Set and enable the interrupt in a block mode operation. The transmit interrupt is set when
the transmit FIFO is below the programmed trigger level. The receive interrupt is set when
the receive FIFO fills to the programmed trigger level. However, the FIFO continues to fill
regardless of the programmed level until the FIFO is full. RXRDYn remains a logic 0 as
long as the FIFO fill level is above the programmed trigger level.
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SC68C652BIB48,128

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NXP Semiconductors
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IC UART DUAL 48LQFP
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