SC68C652B_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 2 November 2009 19 of 43
NXP Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
7.3.2 FIFO mode
Table 11. FIFO Control Register bits description
Bit Symbol Description
7:6 FCR[7:6] RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO equals
the programmed trigger level. However, the FIFO will continue to be loaded
until it is full. Refer to
Table 12.
5:4 FCR[5:4] TX trigger. Logic 0 or cleared is the default condition; TX trigger level = 16.
These bits are used to set the trigger level for the transmit FIFO interrupt.
The SC68C652B will issue a transmit empty interrupt when the number of
characters in FIFO drops below the selected trigger level. Refer to
Table 13.
3 FCR[3] DMA mode select
logic 0 = set DMA mode ‘0’ (normal default condition)
logic 1 = set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC68C652B is in the 16C450
mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs
enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no
characters in the transmit FIFO or transmit holding register, the
TXRDYn pin
will be a logic 0. Once active, the
TXRDYn pin will go to a logic 1 after the
first character is loaded into the transmit holding register.
Receive operation in mode ‘0’: When the SC68C652B is in 16C450 mode,
or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is at
least one character in the receive FIFO, the
RXRDYn pin will be a logic 0.
Once active, the
RXRDYn pin will go to a logic 1 when there are no more
characters in the receiver.
Transmit operation in mode ‘1’: When the SC68C652B is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDYn pin will be a logic 1 when
the transmit FIFO is completely full. It will be a logic 0 when the trigger level
has been reached.
Receive operation in mode ‘1’: When the SC68C652B is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached,
or a Receive Time-Out has occurred, the
RXRDYn pin will go to a logic 0.
Once activated, it will go to a logic 1 after there are no more characters in
the FIFO.
2 FCR[2] XMIT FIFO reset
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
1 FCR[1] RCVR FIFO reset
logic 0 = no FIFO receive reset (normal default condition).
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
0 FCR[0] FIFO enable
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’
when other FCR bits are written to, or they will not be programmed.
