MCP9902T-AE/RW

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P50

MCP9902/3/4

DS20005382C-page 10  2015-2016 Microchip Technology Inc.

4.4 THERM Output

The THERM output is asserted independently of the

ALERT

output and cannot be masked. Whenever any

of the measured temperatures exceed the user

programmed Therm Limit values for the programmed

number of consecutive measurements, the THERM

output is asserted. Once it has been asserted, it will

remain asserted until all measured temperatures drop

below the Therm Limit minus the Therm Hysteresis

(also programmable).

When the THERM

output is asserted, the THERM

status bits will likewise be set. Reading these bits will

not clear them until the THERM output is deasserted.

Once the THERM

output is deasserted, the THERM

status bits will be automatically cleared.

4.5 THERM Pin Address Decoding

The Address decode is performed by pulling known

currents from V

DD

through the external resistor

causing the pin voltage to drop based on the

respective current/resistor relationship. This pin

voltage is compared against a threshold that

determines the value of the pull-up resistor.

The MCP9902/3/4-A SMBus slave address is deter-

mined by the pull-up resistor on the THERM/

ADDR pin

as shown in Ta ble 4-2 .

The MCP9902-1 I

2

C/SMBus address is hard coded to

1001_100(r/w

).

The MCP9902-2 I

2

C/SMBus address is hard coded to

1001_101(r/w

).

The MCP9903-1 I

2

C/SMBus address is hard coded to

1001_100(r/w

).

The MCP9903-2 I

2

C/SMBus address is hard coded to

1001_101(r/w

).

The MCP9904-1 I

2

C/SMBus address is hard coded to

1001_100(r/w

).

The MCP9904-2 I

2

C/SMBus address is hard coded to

1001_101(r/w

).

4.6 ALERT/THERM2 Output

4.6.1 ALERT/THERM2 PIN INTERRUPT

MODE

When configured to operate in interrupt mode, the

ALERT

/THERM2 pin asserts low when an out-of-limit

measurement (>

high limit or < low limit) is detected on

any diode or when an external diode fault is detected.

The ALERT/THERM2 pin will remain asserted as long

as an out-of-limit condition remains. Once the

out-of-limit condition has been removed, the

ALERT

/THERM2 pin will remain asserted until the

appropriate status bits are cleared.

The ALERT

/THERM2 pin can be masked by setting

the MASK_ALL bit. Once the ALERT

/THERM2 pin has

been masked, it will be deasserted and remain deas-

serted until the MASK_ALL bit is cleared by the user.

Any interrupt conditions that occur while the

ALERT/THERM2 pin is masked will update the Status

Register normally. There are also individual channel

masks (see Register 5-20).

The ALERT

/THERM2 pin is used as an interrupt signal

or as an SMBus Alert signal that allows an SMBus

slave to communicate an error condition to the master.

One or more ALERT

/THERM2 Outputs can be

hard-wired together.

4.6.2 ALERT/THERM2 PIN IN THERM

MODE

When the ALERT/THERM2 pin is configured to oper-

ate in THERM mode, it will be asserted if any of the

measured temperatures exceeds the respective high

limit. The ALERT

/THERM2 pin will remain asserted

until all temperatures drop below the corresponding

high limit minus the Therm Hysteresis value.

When the ALERT

/THERM2 pin is asserted in THERM

mode, the corresponding high limit status bits will be

set. Reading these bits will not clear them until the

ALERT

/THERM2 pin is deasserted. Once the

ALERT

/THERM2 pin is deasserted, the status bits will

be automatically cleared.

The MASK_ALL bit will not block the ALERT

/THERM2

pin in this mode; however, the individual channel

masks (see Register 5-20) will prevent the respective

channel from asserting the ALERT

/THERM2 pin.

4.6.3 DEFAULT POWER UP CONDITIONS

On power-up, the ALERT/THERM2 is disabled and the

MASK ALL (MSKAL) bit in the CONFIG register (see

Register 5-6) is set. Additionally, an artificial fault has

been placed in the device, and is enabled at power up.

The FAULT TEST (FT_TST) bit in the Fault Status reg-

ister (see Register 5-20) will allow the assertion of the

ALERT

/THERM2 pin when this test mode is enabled

once MSKAL is cleared. To use the ALERT

/THERM2

functions described in this section, the MSKAL bit must

be set to ‘0’, and the FT_TST bit to ‘1’ in order for the

pin to function properly.

TABLE 4-2: I

2

C/SMBUS ADDRESS

DECODE

Pull Up Resistor on

THERM

pin (±5%)

SMBus Address

4.7 kΩ 1111_100 (r/w

)b

6.8 kΩ 1011_100 (r/w)b

10 kΩ 1001_100 (r/w

)b

15 kΩ 1101_100 (r/w)b

22 kΩ 0011_100 (r/w)b

33 kΩ 0111_100 (r/w

)b

 2015-2016 Microchip Technology Inc. DS20005382C-page 11

MCP9902/3/4

4.7 Temperature Measurement

The MCP9902/3/4 can monitor the temperature of up

to three externally connected diodes.

The device contains programmable High, Low and

Therm limits for all measured temperature channels. If

the measured temperature goes below the Low limit or

above the High limit, the ALERT

/THERM2 pin can be

asserted (based on user settings). If the measured

temperature meets or exceeds the Therm Limit, the

THERM

pin is asserted unconditionally, providing two

tiers of temperature detection.

4.8 Beta Compensation

The MCP9902/3/4 is configured to monitor the

temperature of basic diodes (e.g., 2N3904) or CPU

thermal diodes. For the MCP9902/3/4, the External

Diode 1 channel automatically detects the type of

external diode and determines the optimal setting to

reduce temperature errors introduced by beta variation.

Compensating for this error is also known as

implementing the transistor or BJT model for

temperature measurement.

For discrete transistors configured with the collector and

base shorted together, the beta is generally sufficiently

high such that the percent change in beta variation is

very small. For example, a 10% variation in beta for two

forced emitter currents with a transistor whose ideal

beta is 50 would contribute approximately +0.25°C error

at +100°C. However, for substrate transistors where the

base-emitter junction is used for temperature measure-

ment and the collector is tied to the substrate, the pro-

portional beta variation will cause large error. For

example, a 10% variation in beta for two forced emitter

currents with a transistor whose ideal beta is 0.5 would

contribute approximately +8.25°C error at +100°C.

The MCP9904 does not support Beta Compensation on

External Diode 2 and External Diode 3 channels due to

the high beta of diode-connected transistors.

Care should be taken when setting the BETA<2:0> bits if

the auto-detection circuitry is disabled. If the Beta

Compensation factor is set at a beta value that is higher

than the transistor beta, the circuit may introduce

measurement errors. When measuring a discrete

thermal diode (such as 2N3904) or a CPU diode that

functions like a discrete thermal diode (such as an AMD

processor diode), the BETA<2:0> bits should be set to

‘111b’.

4.9 Resistance Error Correction (REC)

Parasitic resistance in series with the external diodes

will limit the accuracy obtainable from temperature

measurement devices. The voltage developed across

this resistance by the switching diode currents causes

the temperature measurement to read higher than the

true temperature. Contributors to series resistance are

PCB trace resistance, on die (i.e., on the processor)

metal resistance, bulk resistance in the base and emit-

ter of the temperature transistor. Typically, the error

caused by series resistance is +0.7°C per ohm. The

MCP9902/3/4 automatically corrects up to 100 ohms

of series resistance.

4.10 Programmable External Diode

Ideality Factor

The MCP9902/3/4 is designed for external diodes with

an ideality factor of 1.008. Not all external diodes,

processor or discrete, will have this exact value. This

variation of the ideality factor introduces temperature

measurement errors which must be corrected. This

correction is typically done using programmable offset

registers. Since an ideality factor mismatch introduces

an error that is a function of temperature, this correction

is only accurate within a small range of temperatures.

To provide maximum flexibility to the user, the

MCP9902/3/4 provides a 6-bit register for each external

diode where the ideality factor of the diode used is

programmed to eliminate errors across all

temperatures.

These registers store the ideality factors that are

applied to the external diode. Table 4-3 defines each

setting and the corresponding ideality factor. Beta

Compensation and Resistance Error Correction

automatically correct for most diode ideality errors;

therefore, it is not recommended that these settings be

updated without consulting Microchip Technology Inc.

MCP9902/3/4

DS20005382C-page 12  2015-2016 Microchip Technology Inc.

For CPU substrate transistors that require the BJT

transistor model, the ideality factor behaves slightly

differently than for discrete diode-connected

transistors. Refer to Table 4-4 when using a CPU

substrate transistor.

4.11 Diode Faults

The MCP9902/3/4 detects several “diode fault” mech-

anisms, defined as one of the following: an open

between DP and DN, a short from V

DD

to DP, or a

short from V

DD

to DN. When each temperature mea-

surement is made, the device checks for a diode fault

on the external diode channel(s). When a diode fault is

detected, the ALERT

/THERM2 pin asserts (unless

masked, see Register 5-20) and the temperature data

reads 00h in the MSB and LSB registers (note: the low

limit will not be checked).

If a short occurs across DP and DN or a short occurs

from DP to GND, the low limit status bit is set and the

ALERT

/THERM2 pin asserts (unless masked). This

condition is indistinguishable from a temperature

measurement of 0.000°C (-64°C in extended range)

resulting in temperature data of 00h in the MSB and LSB

registers.

If a short from DN to GND occurs (with a diode-con-

nected transistor), temperature measurements will

continue as normal with no alerts.

The External Diode Fault Register (Register 5-19)

indicates which of the external diodes caused the

FAULT bit in the Status Register to be set. This

register is cleared when it is read.

4.12 Consecutive Alerts

The MCP9902/3/4 contains multiple consecutive alert

counters. One set of counters applies to the

ALERT/THERM2 pin and the second set of counters

applies to the THERM

pin. Each temperature measure-

ment channel has a separate consecutive alert counter

for each of the ALERT/THERM2 and THERM pins. All

counters are user programmable and determine the

number of consecutive measurements that a tempera-

ture channel(s) must be out-of-limit or reporting a diode

fault before the corresponding pin is asserted.

The Consecutive Alert register determines how many

times an out-of-limit error or diode fault must be

detected in consecutive measurements before the

ALERT

/THERM2 or THERM pin is asserted. Addition-

ally, the Consecutive Alert register controls the SMBus

Time-out functionality.

An out-of-limit condition (i.e., HIGH, LOW or FAULT)

occurring on the same temperature channel in consec-

utive measurements will increment the consecutive

alert counter. The counters will also be reset if no

out-of-limit condition or diode fault condition occurs in a

consecutive reading.

When the ALERT

/THERM2 pin is configured as an

interrupt, when the consecutive alert counter reaches

its programmed value, the following will occur: the

STATUS bit(s) for that channel and the last error

condition(s) (i.e., E1HIGH, or E2LOW and/or

TABLE 4-3: IDEALITY FACTOR LOOK-UP

TABLE (DIODE MODEL)

Setting Factor Setting Factor Setting Factor

08h 0.9949 18h 1.0159 28h 1.0371

09h 0.9962 19h 1.0172 29h 1.0384

0Ah 0.9975 1Ah 1.0185 2Ah 1.0397

0Bh 0.9988 1Bh 1.0200 2Bh 1.0410

0Ch 1.0001 1Ch 1.0212 2Ch 1.0423

0Dh 1.0014 1Dh 1.0226 2Dh 1.0436

0Eh 1.0027 1Eh 1.0239 2Eh 1.0449

0Fh 1.0040 1Fh 1.0253 2Fh 1.0462

10h 1.0053 20h 1.0267 30h 1.0475

11h 1.0066 21h 1.0280 31h 1.0488

12h 1.0080 22h 1.0293 32h 1.0501

13h 1.0093 23h 1.0306 33h 1.0514

14h 1.0106 24h 1.0319 34h 1.0527

15h 1.0119 25h 1.0332 35h 1.0540

16h 1.0133 26h 1.0345 36h 1.0553

17h 1.0146 27h 1.0358 37h 1.0566

TABLE 4-4: SUBSTRATE DIODE IDEALITY

FACTOR LOOK-UP TABLE

(BJT MODEL)

Setting Factor Setting Factor Setting Factor

08h 0.9869 18h 1.0079 28h 1.0291

09h 0.9882 19h 1.0092 29h 1.0304

0Ah 0.9895 1Ah 1.0105 2Ah 1.0317

0Bh 0.9908 1Bh 1.0120 2Bh 1.0330

0Ch 0.9921 1Ch 1.0132 2Ch 1.0343

0Dh 0.9934 1Dh 1.0146 2Dh 1.0356

0Eh 0.9947 1Eh 1.0159 2Eh 1.0369

0Fh 0.9960 1Fh 1.0173 2Fh 1.0382

10h 0.9973 20h 1.0187 30h 1.0395

11h 0.9986 21h 1.0200 31h 1.0408

12h 1.0000 22h 1.0213 32h 1.0421

13h 1.0013 23h 1.0226 33h 1.0434

14h 1.0026 24h 1.0239 34h 1.0447

15h 1.0039 25h 1.0252 35h 1.0460

16h 1.0053 26h 1.0265 36h 1.0473

17h 1.0066 27h 1.0278 37h 1.0486

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