2015-2016 Microchip Technology Inc. DS20005382C-page 13
MCP9902/3/4
E2FAULT) will be set to ‘1’, the ALERT/THERM2 pin
will be asserted, the consecutive alert counter will be
cleared and measurements will continue.
When the ALERT
/THERM2 pin is configured as a
comparator, the consecutive alert counter will ignore
diode fault and low limit errors and only increment if the
measured temperature exceeds the High Limit.
Additionally, once the consecutive alert counter
reaches the programmed limit, the ALERT
/THERM2
pin will be asserted, but the counter will not be reset. It
will remain set until the temperature drops below the
High Limit minus the Therm Hysteresis value.
For example, if the CALRT<2:0> bits are set for four
consecutive alerts on an MCP9902/3/4 device, the high
limits are set at +70°C and none of the channels are
masked, then the ALERT
/THERM2 pin will be asserted
after the following five measurements:
• The Internal Diode reads +71°C and both the
external diodes read +69°C. Consecutive alert
counter for INT is incremented to 1.
• Both the Internal Diode and the External Diode 1
read +71°C and External Diode 2 reads +68°C.
The consecutive alert counter for INT is incre-
mented to 2 and the counter for EXT1 is set to 1.
• The External Diode 1 reads +71°C and both Inter-
nal Diode and External Diode 2 read +69°C. The
consecutive alert counters for INT and EXT2 are
cleared, and EXT1 is incremented to 2.
• The Internal Diode reads +71°C and both external
diodes read +71°C. The consecutive alert counter
for INT is set to 1, EXT2 is set to 1 and EXT1 is
incremented to 3.
• The Internal Diode reads +71°C and both external
diodes read +71°C. The consecutive alert counter
for INT is incremented to 2, EXT2 is set to 2 and
EXT1 is incremented to 4. The appropriate status
bits are set for EXT1 and the ALERT
/THERM2 pin
is asserted. The EXT1 counter is reset to 0 and all
other counters hold the last value until the next
temperature measurement.
All temperature channels use this value to set the
respective counters. The consecutive Therm counter
is incremented whenever any measurement exceeds
the corresponding Therm Limit.
If the temperature drops below the Therm Limit, the
counter is reset. If a number of consecutive
measurements above the Therm Limit occurs, the
THERM
pin is asserted low.
Once the THERM
pin has been asserted, the
consecutive therm counter will not reset until the
corresponding temperature drops below the Therm
Limit minus the Therm Hysteresis value.
The default setting is one out-of-limit conversion and it is
set in Register 5-21.
4.13 Limit Register Interaction
The various limit registers in the device interact based
on both external conditions present on the diode pins
as well as changes in register bits in the SMBus inter-
face. The device contains both high and low limits for
all temperature channels. If the measured temperature
exceeds the high limit, then the corresponding status
bit is set and the ALERT
/THERM2 pin is asserted.
Likewise, if the measured temperature is less than or
equal to the low limit, the corresponding status bit is
set and the ALERT
/THERM2 pin is asserted.
The data format for the limits must match the selected
data format for the temperature so that if the extended
temperature range is used, the limits must be
programmed in the extended data format.
The limit registers with multiple addresses are fully
accessible at either address.
When the device is in Standby mode, updating the limit
registers will have no effect until the next conversion
cycle occurs. This can be initiated via a write to the
One Shot register (see Register 5-15) or by clearing
the RUN/STOP bit (see Register 5-6).
The THERM
Limit Status register contains the status
bits that are set when a temperature channel Therm
Limit is exceeded. If any of these bits are set, the
THERM
status bit in the Status register is set. Reading
from the THERM
Limit Status register will not clear the
status bits. Once the temperature drops below the
THERM Limit minus the THERM Hysteresis, the corre-
sponding status bits will be automatically cleared. The
THERM
bit in the Status register will be cleared when
all individual channel THERM
bits are cleared.
TABLE 4-5: CONSECUTIVE ALERT/
THERM SETTINGS
210
Number of consecutive out of
limit measurements
000
1
(default for CALRT<2:0>)
001 2
011 3
111
4
(default for CTHRM<2:0>)
