MCP9902/3/4
DS20005382C-page 16 2015-2016 Microchip Technology Inc.
5.0 COMMUNICATIONS
PROTOCOL
The MCP9902/3/4 communicates with a host
controller, such as an PIC MCU, through the SMBus.
The SMBus is a two-wire serial communication
protocol between a computer host and its peripheral
devices. A detailed timing diagram is shown in
Figure 4-1.
For the first 15 ms after power-up the device may not
respond to SMBus communications.
5.1 SMBus Control Bits
The interaction between clock and data creates special
function bits within the data stream.
5.1.1 SMBUS START BIT
The SMBus Start bit is defined as a transition of the
SMBus Data line from a logic ‘1’ state to a logic ‘0’
state while the SMBus Clock line is in a logic ‘1’ state.
5.1.2 SMBUS ADDRESS AND RD/WR BIT
The SMBus Address Byte consists of the 7-bit client
address followed by the RD/WR
indicator bit. If this
RD/WR
bit is a logic ‘0’, the SMBus Host is writing
data to the client device. If this RD/WR
bit is a logic ‘1’,
the SMBus Host is reading data from the client device.
5.1.3 SMBUS DATA BYTES
All SMBus Data bytes are sent most significant bit first
and composed of 8-bits of information.
5.1.4 SMBUS ACK AND NACK BITS
The SMBus client will acknowledge all data bytes that
it receives. This is done by the client device pulling the
SMBus data line low after the 8th bit of each byte that
is transmitted. This applies to the Write Byte protocol.
The Host will NACK (not acknowledge) the last data
byte to be received from the client by holding the
SMBus data line high after the 8th data bit has been
sent.
5.1.5 SMBUS STOP BIT
The SMBus Stop bit is defined as a transition of the
SMBus Data line from a logic ‘0’ state to a logic ‘1’
state while the SMBus clock line is in a logic ‘1’ state.
When the device detects an SMBus Stop bit and it has
been communicating with the SMBus protocol, it will
reset its client interface and prepare to receive further
communications.
5.2 SMBus Timeout
The MCP9902/3/4 supports SMBus Timeout. If the
clock line is held low for longer than t
TIMEOUT
, the
device will reset its SMBus protocol. This function can
be enabled by setting the TIMEOUT bit (see
Register 5-21).
5.3 SMBus and I
2
C Compatibility
The MCP9902/3/4 is compatible with SMBus and I
2
C.
The major differences between SMBus and I
2
C
devices are highlighted here. For more information,
refer to the SMBus 2.0 and I
2
C specifications. For
information on using the MCP9902/3/4 in an I
2
C sys-
tem, refer to AN14.0 “Microchip Dedicated Slave
Devices in I
2
C Systems”, DS00001853.
• MCP9902/3/4 supports I
2
C fast mode at 400 kHz.
This covers the SMBus max time of 100 kHz.
• Minimum frequency for SMBus communications
is 10 kHz.
• The SMBus client protocol will reset if the clock is
held at a logic ‘0’ for longer than 30 ms. This time-
out functionality is disabled by default in the
MCP9902/3/4 and can be enabled by writing to
the TIMEOUT bit. I
2
C does not have a timeout.
•I
2
C devices do not support the Alert Response
Address functionality (which is optional for
SMBus).
Attempting to communicate with the MCP9902/3/4
SMBus interface with an invalid slave address or
invalid protocol will result in no response from the
device and will not affect its register contents. Stretch-
ing of the SMCLK signal is supported, provided other
devices on the SMBus control the timing.
5.4 SMBus Protocols
The device supports Send Byte, Read Byte, Write
Byte, Receive Byte and the Alert Response Address
as valid protocols, as shown below.
All of the following protocols use the convention in
Table 5-1.
TABLE 5-1: PROTOCOL FORMAT
Data Sent To Device Data Sent To The Host
# of bits sent # of bits sent
