M24C16, M24C08, M24C04, M24C02, M24C01 Device operation
Doc ID 5067 Rev 13 13/40
3.5 Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 3 (on Serial Data (SDA), most significant bit first).
The device select code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is
1010b.
Each device is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the
device select code is received, the device only responds if the Chip Enable Address is the
same as the value on the Chip Enable (E0, E1, E2) inputs. However, those devices with
larger memory capacities (the M24C16, M24C08 and M24C04) need more address bits. E0
is not available for use on devices that need to use address line A8; E1 is not available for
devices that need to use address line A9, and E2 is not available for devices that need to
use address line A10 (see Figure 2 and Table 3 for details). Using the E0, E1 and E2 inputs,
up to eight M24C02 (or M24C01), four M24C04, two M24C08 or one M24C16 devices can
be connected to one I²C bus. In each case, and in the hybrid cases, this gives a total
memory capacity of 16 Kbits, 2 KBytes (except where M24C01 devices are used).
The 8
th
bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9
th
bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 4. Operating modes
Mode RW bit WC
(1)
1. X =
V
IH
or V
IL
.
Bytes Initial sequence
Current Address Read 1 X 1 Start, Device Select, RW = 1
Random Address Read
0 X
1
Start, Device Select, RW = 0, Address
1 X reStart, Device Select, RW = 1
Sequential Read 1 X 1
Similar to Current or Random Address
Read
Byte Write 0 V
IL
1 Start, Device Select, RW = 0
Page Write 0 V
IL
16 Start, Device Select, RW = 0
Device operation M24C16, M24C08, M24C04, M24C02, M24C01
14/40 Doc ID 5067 Rev 13
Figure 7. Write mode sequences with WC = 1 (data write inhibited)
3.6 Write operations
Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8, and waits for an
address byte. The device responds to the address byte with an acknowledge bit, and then
waits for the data byte.
When the bus master generates a Stop condition immediately after the Ack bit (in the “10
th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is
triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.
During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and
the device does not respond to any requests.
3.6.1 Byte Write
After the device select code and the address byte, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven High (during
the period from the Start condition until the end of the address byte), the device replies to
the data byte with NoAck, as shown in Figure 7, and the location is not modified. If, instead,
the addressed location is not Write-protected, the device replies with Ack. The bus master
terminates the transfer by generating a Stop condition, as shown in Figure 8.
Stop
Start
Byte Write Dev select Byte address Data in
WC
Start
Page Write Dev select Byte address Data in 1 Data in 2
WC
Data in 3
AI02803d
Page Write
(cont'd)
WC (cont'd)
Stop
Data in N
ACK ACK NO ACK
R/W
ACK ACK NO ACK NO ACK
R/W
NO ACK NO ACK
M24C16, M24C08, M24C04, M24C02, M24C01 Device operation
Doc ID 5067 Rev 13 15/40
3.6.2 Page Write
The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits are the same. If more bytes are sent than will fit up to the end of the
page, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is Low. If the addressed location is Write-protected, by Write
Control (WC) being driven High (during the period from the Start condition until the end of
the address byte), the device replies to the data bytes with NoAck, as shown in Figure 7,
and the locations are not modified. After each byte is transferred, the internal byte address
counter (the 4 least significant address bits only) is incremented. The transfer is terminated
by the bus master generating a Stop condition.
Figure 8. Write mode sequences with WC = 0 (data write enabled)
Stop
Start
Byte Write Dev Select Byte address Data in
WC
Start
Page Write Dev Select Byte address Data in 1 Data in 2
WC
Data in 3
AI02804c
Page Write
(cont'd)
WC (cont'd)
Stop
Data in N
ACK
R/W
ACK ACK
ACK ACK ACK ACK
R/W
ACKACK

M24C02-RDS6G

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
EEPROM 1.8-5.5V 2K (256x8)
Lifecycle:
New from this manufacturer.
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