M24C16, M24C08, M24C04, M24C02, M24C01 DC and AC parameters
Doc ID 5067 Rev 13 25/40
Table 16. AC characteristics at 100 kHz (I
2
C Standard-mode)
(1)
(M24Cxx-W,
M24Cxx-R, M24Cxx-F)
1. Values recommended by the I
2
C bus Standard-mode specification for a robust design of the I
2
C bus
application. Note that the M24xxx devices decode correctly faster timings as specified in Table 15: AC
characteristics at 400 kHz (I2C Fast-mode) (M24Cxx-W, M24Cxx-R, M24Cxx-F).
Test conditions specified in either Table 6, Table 7 or Table 8 and Table 13
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SCL
Clock frequency - 100 kHz
t
CHCL
t
HIGH
Clock pulse width high 4 - µs
t
CLCH
t
LOW
Clock pulse width low 4.7 - µs
t
XH1XH2
t
R
Input signal rise time - 1 µs
t
XL1XL2
t
F
Input signal fall time - 300 ns
t
DL1DL2
(2)
2. Characterized only.
t
F
SDA fall time - 300 ns
t
DXCX
t
SU:DAT
Data in setup time 250 - ns
t
CLDX
t
HD:DAT
Data in hold time 0 - ns
t
CLQX
t
DH
Data out hold time 200 - ns
t
CLQV
(3)
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
t
AA
Clock low to next data valid (access time) 200 3450 ns
t
CHDX
(4)
4. For a reStart condition, or following a Write cycle.
t
SU:STA
Start condition setup time 4.7 - µs
t
DLCL
t
HD:STA
Start condition hold time 4 - µs
t
CHDH
t
SU:STO
Stop condition setup time 4 - µs
t
DHDL
t
BUF
Time between Stop condition and next Start
condition
4.7 - µs
t
W
t
WR
Write time - 5 ms
