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SST26VF016-80-5I-QAE-T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
©2011 Silicon Storage Technology, Inc. DS-25017A 04/11
10
Serial Quad I/O (SQI) Flash Memory
SST26VF016 / SST26VF032
Data Sheet
A
Microchip Technology Company
Write-Enable Latch (WEL)
The Write-Enable Latch (WEL) bit indicates the status of the internal memory’s Write-Enable Latch. If
the WEL bit is set to ‘1’, the device is write enabled. If the bit is set to ‘0’ (reset), the device is not write
enabled and does not accept any memory Program or Erase, Protection Register Write, or Lock-Down
commands. The Write-Enable Latch bit is automatically reset under the following conditions:
• Power-up
• Reset
• Write-Disable (WRDI) instruction completion
• Page-Program instruction completion
• Sector-Erase instruction completion
• Block-Erase instruction completion
• Chip-Erase instruction completion
• Write-Block-Protection register instruction
• Lock-Down Block-Protection register instruction
• Program Security ID instruction completion
• Lockout Security ID instruction completion
• Write-Suspend instruction
Write Suspend Erase Status (WSE)
The Write Suspend-Erase Status (WSE) indicates when an Erase operation has been suspended. The
WSE bit is ‘1’ after the host issues a suspend command during an Erase operation. Once the sus-
pended Erase resumes, the WSE bit is reset to ‘0.’
Write Suspend Program Status (WSP)
The Write Suspend-Program Status (WSP) bit indicates when a Program operation has been sus-
pended. The WSP is ‘1’ after the host issues a suspend command during the Program operation. Once
the suspended Program resumes, the WSP bit is reset to ‘0.’
Write Protection Lockdown Status (WPLD)
The Write Protection-Lockdown Status (WPLD) bit indicates when the Block Protection register is
locked-down to prevent changes to the protection settings. The WPLD is ‘1’ after the host issues a
Lock-Down Block Protection command. After a power cycle, the WPLD bit is reset to ‘0.’
Security ID Status (SEC)
The Security ID Status (SEC) bit indicates when the Security ID space is locked to prevent a Write
command. The SEC is ‘1’ after the host issues a Lockout SID command. Once the host issues a Lock-
out SID command, the SEC bit can never be reset to ‘0.’
Busy
The Busy bit determines whether there is an internal Erase or Program operation in progress. If the
BUSY bit is ‘1’, the device is busy with an internal Erase or Program operation. If the bit is ‘0’, no Erase
or Program operation is in progress.
©2011 Silicon Storage Technology, Inc. DS-25017A 04/11
11
Serial Quad I/O (SQI) Flash Memory
SST26VF016 / SST26VF032
Data Sheet
A
Microchip Technology Company
Instructions
Instructions are used to read, write (erase and program), and configure the SST26VF016/032. The
instruction bus cycles are two nibbles each for commands (Op Code), data, and addresses. Prior to
executing any write instructions, the Write-Enable (WREN) instruction must be executed. The com-
plete list of the instructions is provided in Table 3.
All instructions are synchronized off a high to low transition of CE#. Inputs are accepted on the rising
edge of SCK starting with the most significant nibble. CE# must be driven low before an instruction is
entered and must be driven high after the last nibble of the instruction has been input (except for read
instructions). Any low-to-high transition on CE# before receiving the last nibble of an instruction bus
cycle, will terminate the instruction being entered and return the device to the standby mode.
Table 3: Device Operation Instructions for SST26VF016/032 (1 of 2)
Instruction Description
Command
Cycle
1
Address
Cycle(s)
2
Dummy
Cycle(s)
Data
Cycle(s)
Maximum
Frequency
NOP No Operation 00H 0 0 0
80 MHz
RSTEN Reset Enable 66H 0 0 0
RST
3
Reset Memory 99H 0 0 0
EQIO Enable Quad I/O 38H 0 0 0
RSTQIO
4
Reset Quad I/O FFH 0 0 0
Read
5
Read Memory 03H 3 0 1 to 33 MHz
High-Speed
Read
5
Read Memory at Higher Speed 0BH 3 1 1 to
80 MHz
Set Burst
6
Set Burst Length C0H 0 0 1
Read Burst nB Burst with Wrap 0CH 3 1 n to
Read PI
7
Jump to address within 256
Byte page indexed by n
08H 1 1 1 to
Read I Jump to address within block
indexed by n
09H 2 2 1 to
Read BI Jump to block Indexed by n 10H 1 2 1 to
JEDEC-ID
5,8
JEDEC-ID Read 9FH 0 0 3 to
Quad J-ID
8
Quad I/O J-ID Read AFH 0 0 3 to
Sector Erase
9
Erase 4 KBytes of Memory Array 20H 3 0 0
Block Erase
10
Erase 64, 32 or 8 KBytes of
Memory Array
D8H 3 0 0
Chip Erase Erase Full Array C7H 0 0 0
Page Program Program 1 to 256 Data Bytes 02H 3 0 1 to 256
Write Suspend Suspends Program/Erase B0H 0 0 0
Write Resume Resumes Program/Erase 30H 0 0 0
Read SID Read Security ID 88H 1 1 1 to 32
Program SID
11
Program User Security ID area A5H 1 0 1 to 24
Lockout SID
11
Lockout Security ID Programming
85H 0 0 0
RDSR
12
Read Status Register 05H 0 0 1 to
WREN Write Enable 06H 0 0 0
WRDI Write Disable 04H 0 0 0
©2011 Silicon Storage Technology, Inc. DS-25017A 04/11
12
Serial Quad I/O (SQI) Flash Memory
SST26VF016 / SST26VF032
Data Sheet
A
Microchip Technology Company
No Operation (NOP)
The No Operation command only cancels a Reset Enable command. NOP has no impact on any other
command.
RBPR
13
Read Block Protection Register 72H 0 0 1 tom/4
80 MHz
WBPR
11,13
Write Block Protection Register 42H 0 0 1 to m/4
LBPR
11
Lock Down Block Protection
Register
8DH 0 0 0
T3.0 25017
1. One BUS cycle is two clock periods (command, access, or data).
2. Address bits above the most significant bit of each density can be V
IL
or V
IH.
3. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.
4. Device accepts eight-clock command in SPI mode, or two-clock command in SQI mode.
5. After a power cycle, Read, High-Speed Read, and JEDEC-ID Read instructions input and output cycles are SPI bus
protocol.
6. Burst length–n=8Bytes: Data(00H);n=16Bytes: Data(01H);n=32Bytes: Data(02H);n=64Bytes: Data(03H).
7. Address is 256 Bytes page align (2’s complement)
8. The Quad J-ID read wraps the three Quad J-ID Bytes of data until terminated by a low-to-high transition on CE#
9. Sector Addresses: Use A
MS
-A
12
, remaining address are don’t care, but must be set to V
IL
or V
IH
.
10. Blocks are 64 KByte, 32 KByte, or 8KByte, depending on location. Block Erase Address: A
MS
-A
16
for 64 KByte; A
MS
-
A
15
for 32 KByte; A
MS
-A
13
for 8 KByte. Remaining addresses are don’t care, but must be set to V
IL
or V
IH
.
11. Requires a prior WREN command.
12. The Read-Status register is continuous with ongoing clock cycles until terminated by a low-to-high transition on CE#.
13. Data is written/read from MSB to LSB. MSB = 48 for SST26VF016; 80 for SST26VF032
Table 3: Device Operation Instructions for SST26VF016/032 (Continued) (2 of 2)
Instruction Description
Command
Cycle
1
Address
Cycle(s)
2
Dummy
Cycle(s)
Data
Cycle(s)
Maximum
Frequency
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39

SST26VF016-80-5I-QAE-T

Mfr. #:
Buy SST26VF016-80-5I-QAE-T
Manufacturer:
Microchip Technology
Description:
NOR Flash 2.7 to 3.6V 16Mbit Serial Quad I/O Flsh
Lifecycle:
New from this manufacturer.
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