©2011 Silicon Storage Technology, Inc. DS-25017A 04/11
19
Serial Quad I/O (SQI) Flash Memory
SST26VF016 / SST26VF032
Data Sheet
A
Microchip Technology Company
Quad J-ID Read (SQI Protocol)
The Quad J-ID Read instruction identifies the devices as SST26VF016/032 and manufacturer as SST.
To execute a Quad J-ID operation the host drives CE# low and then sends the Quad J-ID command
cycle (AFH). Each cycle is two nibbles (clocks) long, most significant nibble first.
Immediately following the command cycle the device outputs data on the falling edge of the SCK sig-
nal. The data output stream is continuous until terminated by a low-to-high transition of CE#. The
device outputs three bytes of data: manufacturer, device type, and device ID, see Table 6. See Figure
14 for instruction sequence.
Figure 14:Quad J-ID Read Sequence
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4 KByte sector to ‘1,’ but it does not change
a protected memory area. Prior to any write operation, the Write-Enable (WREN) instruction must be
executed.
To execute a Sector-Erase operation, the host drives CE# low, then sends the Sector Erase command
cycle (20H) and three address cycles, and then drives CE# high. Each cycle is two nibbles, or clocks,
long, most significant nibble first. Address bits [A
MS
:A
12
](A
MS
= Most Significant Address) determine
the sector address (SA
X
); the remaining address bits can be V
IL
or V
IH
. Poll the BUSY bit in the Status
register or wait T
SE
for the completion of the internal, self-timed, Sector-Erase operation. See Figure
15 for the Sector-Erase sequence.
Figure 15:4 KByte Sector-Erase Sequence
1359 F39.0
MODE 3 0
SCK
SIO(3:0)
CE#
C1 C0
MODE 0
2
H0 L0
MSN
LSN
4
H1 L1
6
H2 L2
8
H0 L0
10
H1 L4
12
H2 L2
N
HN LN
BFH
N
26H De vice ID BFH 26H Device ID
Note: MSN = Most significant Nibble; LSN= Least Significant Nibble
C[1:0]=AFH
1359 F07.0
MODE 3 0 1
SCK
SIO(3:0)
CE#
C1 C0
MODE 0
2
A5 A4
MSN
LSN
4
A3 A2
6
A1 A0
Note: MSN = Most Significant
Nibble, LSN = Least Signifi-
cant Nibble
©2011 Silicon Storage Technology, Inc. DS-25017A 04/11
20
Serial Quad I/O (SQI) Flash Memory
SST26VF016 / SST26VF032
Data Sheet
A
Microchip Technology Company
Block-Erase
The Block-Erase instruction clears all bits in the selected block to ‘1’. Block sizes can be 8 KByte, 32
KByte or 64 KByte depending on address, see Figure 3, Memory Map, for details. A Block-Erase
instruction applied to a protected memory area will be ignored. Prior to any write operation, execute
the WREN instruction. Keep CE# active low for the duration of any command sequence.
To execute a Block-Erase operation, the host drives CE# low then sends the Block-Erase command
cycle (D8H), three address cycles, then drives CE# high. Each cycle is two nibbles, or clocks, long,
most significant nibble first. Address bits A
MS
-A
13
determine the block address; the remaining address
bits can be V
IL
or V
IH
. For 32 KByte blocks, A
14
:A
13
can be V
IL
or V
IH
; for 64 KByte blocks, A
15
:A
13
can
be V
IL
or V
IH
. Poll the BUSY bit in the Status register or wait T
BE
for the completion of the internal, self-
timed, Block-Erase operation See Figure 16 for the Block-Erase sequence.
Figure 16:Block-Erase Sequence
Chip-Erase
The Chip-Erase instruction clears all bits in the device to ‘1.’ The Chip-Erase instruction is ignored if
any of the memory area is protected. Prior to any write operation, execute the the WREN instruction.
To execute a Chip-Erase operation, the host drives CE# low, sends the Chip-Erase command cycle
(C7H), then drives CE# high. A cycle is two nibbles, or clocks, long, most significant nibble first. Poll the
BUSY bit in the Status register or wait T
CE
for the completion of the internal, self-timed, Chip-Erase
operation. See Figure 17 for the Chip Erase sequence.
Figure 17:Chip-Erase Sequence
1359 F08.0
MODE 3 0 1
SCK
SIO(3:0)
CE#
C1 C0
MODE 0
2
A5 A4
MSN
LSN
4
A3 A2
6
A1 A0
Note: MSN = Most Significant Nibble,
LSN = Least Significant Nibble
C[1:0] = D8H
1359 F09.0
MODE 3 0 1
SCK
SIO(3:0)
CE#
C1 C0
MODE 0
Note: C[1:0] = C7H
©2011 Silicon Storage Technology, Inc. DS-25017A 04/11
21
Serial Quad I/O (SQI) Flash Memory
SST26VF016 / SST26VF032
Data Sheet
A
Microchip Technology Company
Page-Program
The Page-Program instruction programs up to 256 Bytes of data in the memory. The data for the
selected page address must be in the erased state (FFH) before initiating the Page-Program operation.
A Page-Program applied to a protected memory area will be ignored. Prior to the program operation,
execute the WREN instruction.
To execute a Page-Program operation, the host drives CE# low then sends the Page Program com-
mand cycle (02H), three address cycles followed by the data to be programmed, then drives CE# high.
The programmed data must be between 1 to 256 Bytes and in whole Byte increments; sending an odd
number of nibbles will cause the last nibble to be ignored. Each cycle is two nibbles (clocks) long, most
significant bit first. Poll the BUSY bit in the Status register or wait T
PP
for the completion of the internal,
self-timed, Page-Program operation. See Figure 18 for the Page-Program sequence.
When executing Page-Program, the memory range for the SST26VF016/032 is divided into 256 Byte
page boundaries. The device handles shifting of more than 256 Bytes of data by maintaining the last
256 Bytes of data as the correct data to be programmed. If the target address for the Page-Program
instruction is not the beginning of the page boundary (A7:A0 are not all zero), and the number of data
input exceeds or overlaps the end of the address of the page boundary, the excess data inputs wrap
around and will be programmed at the start of that target page.
Figure 18:Page-Program Sequence
Write-Suspend and Write-Resume
Write-Suspend allows the interruption of Sector-Erase, Block-Erase or Page-Program operations in
order to erase, program, or read data in another portion of memory. The original operation can be con-
tinued with the Write-Resume command.
Only one write operation can be suspended at a time; if an operation is already suspended, the device
will ignore the Write-Suspend command. Write-Suspend during Chip-Erase is ignored; Chip-Erase is
not a valid command while a write is suspended.
1359 F10.0
MODE 3 0
SCK
SIO(3:0)
CE#
C1 C0
MODE 0
2
A5 A4
MSN
LSN
4
A3 A2
6
A1 A0
8
H0 L0
10
H1 L1
12
H2 L2
542
HN LN
Data Byte 0
Data Byte 1 Data Byte 2
Data Byte 255
Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble
C[1:0] = 02H

SST26VF016-80-5I-QAE-T

Mfr. #:
Manufacturer:
Microchip Technology
Description:
NOR Flash 2.7 to 3.6V 16Mbit Serial Quad I/O Flsh
Lifecycle:
New from this manufacturer.
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