SI5017-BM Datasheet SI5017-D-GM, SI5017-D-GMR, SI5017-BM | P1-P3

Si5017

OC-48/STM-16 SONET/SDH CDR IC WITH LIMITING AMPLIFIER

Features

High-speed clock and data recovery device with integrated limiting amplifier:

Applications

Description

The Si5017 is a fully-integrated, high-performance limiting amplifier (LA) and clock

and data recovery (CDR) IC for high-speed serial communication systems. It

derives timing information and data from a serial input at OC-48 and STM-16 rates.

Support for 2.7 Gbps data streams is also provided for OC-48/STM-16 applications

that employ forward error correction (FEC). Use of an external reference clock is

optional. Silicon Laboratories® DSPLL

™

technology eliminates sensitive noise

entry points, thus making the PLL less susceptible to board-level interaction and

helping to ensure optimal jitter performance.

The Si5017 represents a new standard in low jitter, low power, small size, and

integration for high-speed LA/CDRs. It operates from a 3.3 V supply over the

industrial temperature range (–40 to 85 °C).

Functional Block Diagram

! Supports OC-48/STM-16 and

2.7 Gbps FEC

! DSPLL™ technology

! Low power—528 mW (typ)

! Small footprint: 5 x 5 mm

! Bit-error-rate alarm

! Jitter generation 3.0 mUI

rms

(typ)

! Loss-of-signal level alarm

! Data slicing level control

! 10 mV

differential sensitivity

! 3.3 V supply

! Reference and reference-less

operation supported

! SONET/SDH/ATM routers

! Add/drop multiplexers

! Digital cross connects

! Board level serial links

! SONET/SDH test equipment

! Optical transceiver modules

! SONET/SDH regenerators

Limiting

Amp

DSPLL

Lock

Detection

Retimer

Reset/

Calibration

Bias Gen.

BUF

CLKOUT+

CLKOUT–

DIN+

DIN–

REFCLK+

REFCLK–

(Optional)

LOS

LOL

REXT

RESET/CAL

SLICE_LVL

DSQLCH

CLK_DSBL

LTR

Signal

Detect

LOS_LVL

BER_LVL

BER

Monitor

DOUT+

DOUT–

BER_ALM

Ordering Information:

See page 22.

Pin Assignments

Si5017

GND

Pad

VDD

LOS_LVL

REFCLK+

VDD

SLICE_LVL

LOL

REFCLK–

REXT

RESET/CAL

DOUT+

VDD

TDI

DOUT–

8 9 10 11 12

LOS

DSQLCH

DIN+

LTR

VDD

13 14

VDD

DIN–

28 27 26 25 24

BER_ALM

BER_LVL

CLKDSBL

VDD

23 22

CLKOUT–

CLKOUT+

Si5017

2 Rev. 1.2

Si5017

Rev. 1.2 3

TABLE OF CONTENTS

Section Page

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Operation Without an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Operation With an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Lock-to-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Loss-of-Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Bit-Error-Rate (BER) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Data Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

RESET/DSPLL Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Pin Descriptions: Si5017 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

SI5017-BM

Mfr. #:

Buy SI5017-BM

Manufacturer:

Silicon Labs

Description:

IC CLOCK/DATA RECOVERY 28MLP

Lifecycle:

New from this manufacturer.

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SI5017-BM

SI5017-BM

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