SI5017-BM Datasheet SI5017-D-GM, SI5017-D-GMR, SI5017-BM | P13-P15

Si5017

Rev. 1.2 13

Lock Detect

The Si5017 provides lock-detect circuitry that indicates

whether the PLL has achieved frequency lock with the

incoming data. The operation of the lock-detector

depends on the reference clock option used.

When an external reference clock is provided, the circuit

compares the frequency of a divided-down version of

the recovered clock with the frequency of the applied

reference clock (REFCLK). If the recovered clock

frequency deviates from that of the reference clock by

the amount specified in Table 4 on page 9, the PLL is

declared out of lock, and the loss-of-lock (LOL

) pin is

asserted. In this state, the PLL will periodically try to

reacquire lock with the incoming data stream. During

reacquisition, the recovered clock frequency (CLKOUT)

drifts over a ±600 ppm range relative to the applied

reference clock and the LOL output alarm may toggle

until the PLL has reacquired frequency lock. Due to the

low noise and stability of the DSPLL, there is the

possibility that the PLL will not drift enough to render an

out-of-lock condition, even if the data is removed from

inputs.

In applications requiring a more stable output clock

during out-of-lock conditions, the lock-to-reference

(LTR

) input can be used to force the PLL to lock to the

externally supplied reference.

In the absence of an external reference, the lock detect

circuitry uses a data quality measure to determine when

frequency lock has been lost with the incoming data

stream. During reacquisition, CLKOUT may vary by

approximately ±10% from the nominal data rate.

Lock-to-Reference

The LTR input is used to force a stable output clock

when an alarm condition, like LOS, exists. In typical

applications, the LOS

output is tied to the LTR input to

force a stable output clock when the input data signal is

lost. When LTR

is asserted, the DSPLL is prevented

from acquiring the data signal present on DIN. The

operation of the LTR

control input depends on which

reference clocking mode is used.

When an external reference clock is present, assertion

of LTR

forces the DSPLL to lock CLKOUT to the

provided reference. If no external reference clock is

used, LTR

forces the DSPLL to hold the digital

frequency control input to the VCO at the last value.

This produces a stable output clock as long as supply

and temperature are constant.

Loss-of-Signal

The Si5017 indicates a loss-of-signal condition on the

LOS

output pin when the input peak-to-peak signal level

on DIN falls below an externally controlled threshold.

The LOS threshold range is specified in Table 3 and is

set by applying a voltage on the LOS_LVL pin. The

graph in Figure 6 illustrates the LOS_LVL mapping to

the LOS threshold. The LOS

output is asserted when

the input signal drops below the programmed peak-to-

peak value. If desired, the LOS

function may be

disabled by grounding LOS_LVL or by adjusting

LOS_LVL to be less than 1 V.

Figure 6. LOS_LVL Mapping

Figure 7. LOS Signal Hysteresis

Table 7. Typical REFCLK Frequencies

SONET/SDH

OC-48 with

15/14 FEC

Ratio of VCO

to REFCLK

19.44 MHz 20.83 MHz 128

77.76 MHz 83.31 MHz 32

155.52 MHz 166.63 MHz 16

40 mV/V

0 mV

0 V

LOS_LVL (V)

LOS Threshold (mV

)

30 mV

2.25 V1.50 V1.00 V

15 mV

LOS Disabled

LOS

Undefined

1.875 V

40 mV

2.5 V

LOS

LOS_LVL

R2 10k

Si5017

CDR

LOS Alarm

Set LOS

Level

Si5017

14 Rev. 1.2

In many applications it is desirable to produce a fixed

amount of signal hysteresis for an alarm indicator such

as LOS

, since a marginal data input signal could cause

intermittent toggling, leading to false alarm status.

When it is anticipated that very low-level DIN signals will

be encountered, the introduction of an adequate

amount of LOS hysteresis is recommended to minimize

any undesirable LOS signal toggling. Figure 7 illustrates

a simple circuit that may be used to set a fixed level of

LOS signal hysteresis for the Si5017 CDR. The value of

R1 may be chosen to provide a range of hysteresis from

3 to 8 dB where a nominal value of 800 Ω adjusts the

hysteresis level to approximately 6 dB. Use a value of

500 Ω or 1000 Ω for R1 to provide 3 dB or 8 dB of

hysteresis, respectively.

Hysteresis is defined as the ratio of the LOS

deassert

level (LOSD) and the LOS

assert level (LOSA). The

hysteresis in decibels is calculated as 20log(LOSD/

LOSA).

Bit-Error-Rate (BER) Detection

The Si5017 uses a proprietary Silicon Laboratories®

algorithm to generate a bit-error-rate (BER) alarm on

the BER_ALM

pin if the observed BER is greater than a

user programmable threshold. Bit error detection relies

on the input data edge timing; edges occurring outside

of the expected event window are counted as bit errors.

The BER threshold is programmed by applying a

voltage to the BER_LVL pin between 500 mV and

2.25 V corresponding to a BER of approximately 10

–10

and 10

–6

, respectively. The voltage present on

BER_LVL maps to the BER as follows: log10(BER) =

(4 x BER_LVL) –13. (BER_LVL is in volts; BER is in bits

per second.)

Data Slicing Level

The Si5017 provides the ability to externally adjust the

slicing level for applications that require bit-error-rate

(BER) optimization. Adjustments in slicing level of

±15 mV (relative to the internally set input common

mode voltage) are supported. The slicing level is set by

applying a voltage between 0.75 and 2.25 V to the

SLICE_LVL input. The voltage present on SLICE_LVL

maps to the slicing level as follows:

where V

SLICE

is the slicing level, and V

SLICE_LVL

is the

voltage applied to the SLICE_LVL pin.

When SLICE_LVL is driven below 500 mV, the slicing

level adjustment is disabled, and the slicing level is set

to the cross-point of the differential input signal.

PLL Performance

The PLL implementation used in the Si5017 is fully

compliant with the jitter specifications proposed for

SONET/SDH equipment by Bellcore GR-253-CORE,

Issue 3, September 2000 and ITU-T G.958.

Jitter Tolerance

The Si5017’s tolerance to input jitter exceeds that of the

Bellcore/ITU mask shown in Figure 8. This mask

defines the level of peak-to-peak sinusoid jitter that

must be tolerated when applied to the differential data

input of the device.

Figure 8. Jitter Tolerance Specification

Jitter Transfer

The Si5017 exceeds all relevant Bellcore/ITU

specifications related to SONET/SDH jitter transfer.

Jitter transfer is defined as the ratio of output signal jitter

to input signal jitter as a function of jitter frequency.

These measurements are made with an input test signal

that is degraded with sinusoidal jitter whose magnitude

is defined by the mask in Figure 9.

SLICE

SLICE_LVL

1.5 V–()

-------------------------------------------------------

1.5

0.15

f0 f1 f2 f3 ft

Sinusoidal

Input

Jitter (UI

)

Frequency

Slope = 20 dB/Decade

(Hz)

(kHz)

SONET

Data Rate

OC-48

(kHz)

10 600 6 100 1000

Si5017

Rev. 1.2 15

Figure 9. Jitter Transfer Specification

Jitter Generation

The Si5017 exceeds all relevant specifications for jitter

generation proposed for SONET/SDH equipment. The

jitter generation specification defines the amount of jitter

that may be present on the recovered clock and data

outputs when a jitter free input signal is provided. The

Si5017 typically generates less than 3.0 mUI

rms

of jitter

when presented with jitter-free input data.

RESET/DSPLL Calibration

The Si5017 achieves optimal jitter performance by

automatically calibrating the loop gain parameters within

the DSPLL on powerup. Calibration may also be

initiated by a high-to-low transition on the RESET/CAL

pin. The RESET/CAL pin must be held high for at least

µs. When RESET/CAL is released (set to low) the

digital logic resets to a known initial condition,

recalibrates the DSPLL, and begins to lock to the

incoming data stream. For a valid reset to occur when

using Reference mode, a proper, external reference

clock frequency must be applied as specified in Table 7.

Clock Disable

The Si5017 provides a clock disable pin (CLK_DSBL)

that is used to disable the recovered clock output

(CLKOUT). When the CLK_DSBL pin is asserted, the

positive and negative terminals of CLKOUT are tied to

VDD through 100 Ω on-chip resistors.

Data Squelch

The Si5017 provides a data squelching pin (DSQLCH)

that is used to set the recovered data output (DOUT) to

binary zero. When the DSQLCH pin is asserted, the

DOUT+ signal is held low and the DOUT– signal is held

high. This pin can be is used to squelch corrupt data

during LOS and LOL situations. Care must be taken

when ac coupling these outputs; a long string of zeros

or ones will not be held through ac coupling capacitors.

Device Grounding

The Si5017 uses the GND pad on the bottom of the 28-

pin micro leaded package (MLP) for device ground. This

pad should be connected directly to the analog supply

ground. See Figure 15 on page 19 and Figure 16 on

page 23 for the ground (GND) pad location.

Bias Generation Circuitry

The Si5017 makes use of an external resistor to set

internal bias currents. The external resistor allows

precise generation of bias currents which significantly

reduces power consumption versus traditional

implementations that use an internal resistor. The bias

generation circuitry requires a 10 kΩ (1%) resistor

connected between REXT and GND.

Voltage Regulator

The Si5017 operates from a 3.3 V external supply

voltage. Internally the device operates from a 2.5 V

supply. The Si5017 regulates 2.5 V internally down from

the external 3.3 V supply.

In addition to supporting 3.3 V systems, the on-chip

linear regulator offers better power supply noise

rejection versus a direct 2.5 V supply.

Differential Input Circuitry

The Si5017 provides differential inputs for both the high-

speed data (DIN) and the reference clock (REFCLK)

inputs. An example termination for these inputs is

shown in Figures 10 and 11, respectively. In

applications where direct dc coupling is possible, the

0.1 µF capacitors may be omitted. (LOS operation is

only guaranteed when ac coupled.) The data input

limiting amplifier requires an input signal with a

differential peak-to-peak voltage as specified in Table 2

on page 7 to ensure a BER of at least 10

–12

. The

REFCLK input differential peak-to-peak voltage

requirement is also specified in Table 2.

0.1 dB

Jitter

Transfer

Frequency

20 dB/Decade

Slope

(kHz)

SONET

Data Rate

OC-48 2000

Acceptable

Range

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

SI5017-BM

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IC CLOCK/DATA RECOVERY 28MLP

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SI5017-BM

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