Si5017
20 Rev. 1.2
7
LOL
OLVTTLLoss-of-Lock.
This output is driven low when the recovered clock
frequency deviates from the reference clock by the
amount specified in Table 4 on page 9. If no exter-
nal reference is supplied, this signal will be active
when the internal PLL is no longer locked to the
incoming data.
8
LTR
ILVTTLLock-to-Reference.
When this pin is low, the DSPLL disregards the data
inputs. If an external reference is supplied, the out-
put clock locks to the supplied reference. If no
external reference is used, the DSPLL locks the
control loop until LTR is released.
Note: This input has a weak internal pullup.
9
LOS
OLVTTLLoss-of-Signal.
This output pin is driven low when the input signal is
below the threshold set via LOS_LVL. (LOS opera-
tion is guaranteed only when ac coupling is used on
the DIN inputs.)
10 DSQLCH LVTTL
Data Squelch.
When driven high, this pin forces the data present
on DOUT+ to zero and DOUT– to one. For normal
operation, this pin should be low. DSQLCH may be
used during LOS/LOL conditions to prevent random
data from being presented to the system.
Note: This input has a weak internal pulldown.
12
13
DIN+
DIN–
ISee Table2Differential Data Input.
Clock and data are recovered from the differential
signal present on these pins. AC coupling is
recommended.
15 GND GND
Production Test Input.
This pin is used during production testing and must
be tied to GND for normal operation.
16
17
DOUT–
DOUT+
OCML
Differential Data Output.
The data output signal is a retimed version of the
data recovered from the signal present on DIN. It is
phase aligned with CLKOUT and is updated on the
rising edge of CLKOUT.
19 RESET/CAL I LVTTL
Reset/Calibrate.
Driving this input high for at least 1 µs will reset
internal device circuitry. A high to low transition on
this pin will force a DSPLL calibration. For normal
operation, drive this pin low.
Note: This input has a weak internal pulldown.
Table 8. Si5017 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Level Description
