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SI5017-BM

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
Si5017
Rev. 1.2 7
Table 2. DC Characteristics
(V
DD
= 3.3 V ±5%, T
A
= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Supply Current
1
FEC (2.7 Gbps)
OC-48
I
DD
—
—
163
160
174
170
mA
Power Dissipation
FEC (2.7 Gbps)
OC-48
P
D
—
—
538
528
603
554
mW
Common Mode Input Voltage (DIN)
2
V
ICM
See Figure 11 1.40 1.50 1.60 V
Common Mode Input Voltage (REFCLK)
2
V
ICM
See Figure 10 1.90 2.10 2.30 V
DIN Single-ended Input Voltage Swing
2
V
IS
See Figure 1A 10 — 500 mV
DIN Differential Input Voltage Swing
2
V
ID
See Figure 1B 10 — 1000 mV
REFCLK Single-ended Input Voltage Swing
2
V
IS
See Figure 1A 200 — 750 mV
REFCLK Differential Input Voltage Swing
2
V
ID
See Figure 1B 200 — 1500 mV
Input Impedance (DIN) R
IN
Line-to-Line 84 100 116 Ω
Differential Output Voltage Swing
(DOUT)
V
OD
100 Ω Load
Line-to-Line
700 800 900 mV
PP
Differential Output Voltage Swing
(CLKOUT)
V
OD
100 Ω Load
Line-to-Line
700 800 900 mV
PP
Output Common Mode Voltage (DOUT) V
OCM
100 Ω Load
Line-to-Line
1.85 1.95 2.00 V
Output Common Mode Voltage (CLKOUT) V
OCM
100 Ω Load
Line-to-Line
1.75 1.80 1.90 V
Output Impedance (DOUT,CLKOUT) R
OUT
Single-ended 84 100 116 Ω
Input Voltage Low (LVTTL Inputs) V
IL
——.8 V
Input Voltage High (LVTTL Inputs) V
IH
2.0 — — V
Input Low Current (LVTTL Inputs) I
IL
——10µA
Input High Current (LVTTL Inputs) I
IH
——10µA
Input Impedance (LVTTL Inputs) R
IN
10 — — kΩ
LOS_LVL, BER_LVL, SLICE_LVL
Input Impedance
R
IN
75 100 125 kΩ
Output Voltage Low (LVTTL Outputs) V
OL
I
O
=2mA — — 0.4 V
Output Voltage High (LVTTL Outputs) V
OH
I
O
=2mA 2.0 — — V
Notes:
1. No load on LVTTL outputs.
2. These inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input must be ac
coupled to ground.
Si5017
8 Rev. 1.2
Table 3. AC Characteristics (Clock and Data)
(V
DD
= 3.3 V ±5%, T
A
= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Output Clock Rate f
CLK
2.4 — 2.7 GHz
Output Clock Rise Time t
R
Figure 3 — 70 90 ps
Output Clock Fall Time t
F
Figure 3 — 70 90 ps
Output Clock Duty Cycle 48 50 52 % of
UI
Output Data Rise Time t
R
Figure 3 — 80 110 ps
Output Data Fall Time t
F
Figure 3 — 80 110 ps
Clock to Data Delay
FEC (2.7 Gbps)
OC-48
t
Cr-D
Figure 2
180
200
215
230
250
260
ps
Clock to Data Delay
FEC (2.7 Gbps)
OC-48
t
Cf-D
Figure 2
–60
–60
–30
–30
0
0
ps
Input Return Loss 100 kHz–1.5 GHz
1.5 GHz–4.0 GHz
–15
–10
—
—
—
—
dB
dB
Slicing Level Offset
1
(relative to the internally set input
common mode voltage)
V
SLICE
SLICE_LVL = 750 mV to
2.25 V
–15 — 15 mV
Slicing Level Accuracy SLICE_LVL = 750 mV to
2.25 V
–500 — 500
µV
Loss-of-Signal Range
2
(peak-to-peak differential)
V
LOS
LOS_LVL = 1.50 to 2.50 V 0 — 40 mV
Loss-of-Signal Response Time t
LOS
Figure 5 8 20 25 µs
Notes:
1. Adjustment voltage (relative to the internally set input common mode voltage) is calculated as follows:
V
SLICE
= (SLICE_LVL – 1.50)/50.
2. Adjustment voltage is calculated as follows: V
LOS
= (LOS_LVL – 1.50)/25.
Si5017
Rev. 1.2 9
Table 4. AC Characteristics (PLL Characteristics)
(V
DD
=3.3 V ±5%, T
A
= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Jitter Tolerance
(OC-48)*
J
TOL(PP)
f = 600 Hz 40 — — UI
PP
f = 6000 Hz 4 — — UI
PP
f = 100 kHz 4 — — UI
PP
f = 1 MHz 0.5 — — UI
PP
RMS Jitter Generation
*
J
GEN(rms)
with no jitter on serial data — 3.0 5.0 mUI
Peak-to-Peak Jitter Generation
*
J
GEN(PP)
with no jitter on serial data — 25 55 mUI
Jitter Transfer Bandwidth
*
J
BW
OC-48 — — 2.0 MHz
Jitter Transfer Peaking
*
J
P
—0.030.1dB
Acquisition Time
(Reference clock applied)
T
AQ
After falling edge of
RESET/CAL
—1.61.9ms
From the return of valid
data
20 100 500
µs
Acquisition Time
(Reference-less operation)
T
AQ
After falling edge of
RESET/CAL
—2.04.5ms
From the return of valid
data
1.5 2.5 5.5 ms
Reference Clock Range 19.44 — 168.75 MHz
Input Reference Clock Frequency
Tolerance
C
TOL
–100 — 100 ppm
Frequency Difference at which
Receive PLL goes out of Lock
(REFCLK compared to the divided
down VCO clock)
450 600 750 ppm
Frequency Difference at which
Receive PLL goes into Lock
(REFCLK compared to the divided
down VCO clock)
150 300 450 ppm
*Note: As defined in Bellcore specifications: GR-253-CORE, Issue 3, September 2000. Using PRBS 2
23
– 1 data pattern.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

SI5017-BM

Mfr. #:
Buy SI5017-BM
Manufacturer:
Silicon Labs
Description:
IC CLOCK/DATA RECOVERY 28MLP
Lifecycle:
New from this manufacturer.
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