LTC3300-2
21
33002f
For more information www.linear.com/LTC3300-2
sipation. The internal component of the DC load current
is dominated by the average gate driver current(s) (G1S
through G6S), each approximated by C • V • f, where C
is the gate capacitance of the external NMOS transistor,
V = V
REG
= 4.8V, and f is the frequency that the gate
driver output is running at. FET manufacturers usually
specify the C • V product as Q
g
(gate charge) measured
in coulombs at a given gate drive voltage. The frequency,
f, is dependent on many terms, primarily the voltage of
each individual cell, the number of cells in the secondary
stack, the programmed peak balancing current, and the
transformer primary and secondary winding inductances.
In a typical application, the C • V • f current loading the
V
REG
output is expected to be low single-digit milliamperes
per driver. Note that the V
REG
loading current is ultimately
delivered from the C6 pin. For applications involving very
large balance currents and/or employing external NMOS
transistors with very large gate capacitance, the V
REG
output may need to source more than 40mA average. For
information on how to design for these situations, refer
to the Applications Information section.
One additional function slaved
to the V
REG
output is
the power-on reset (POR). During initial power-up and
subsequently if the V
REG
pin voltage ever falls below ap-
proximately 4V (e.g., due
to overloading), the serial port
is cleared to the default power-up state with no balancers
active. This feature thus guarantees that the minimum gate
drive provided to the external secondary side FETs is also
4V. For a 10µF capacitor loading the output at initial power-
up, the output reaches regulation in approximately 1ms.
Thermal Shutdown
The LTC3300-2 has an overtemperature protection circuit
which shuts down all active balancing if the internal silicon
die temperature rises to approximately 155°C. When in
thermal shutdown, all serial communication remains active
and the cell balancer status (which contains temperature
information) can be read back. The balance command
which had been being executed remains stored in memory.
This function has 10°C of hysteresis so that when the die
temperature subsequently falls to approximately 145°C,
active balancing will resume with the previously execut
-
ing command.
W
atchdog T
imer Circuit
The watchdog timer circuit provides a means of shutting
down all active balancing in the event that communication
to the LTC3300-2 is lost. The watchdog timer
initiates
when
a balance command begins executing and is reset
to zero every time a valid 8-bit command byte (see Serial
Port Operation) is written. The valid command byte can
be an execute, a write, or a read (command or status).
“Partial” reads and writes are considered valid, i.e., it is
only necessary that the first 8 bits have to be written and
contain the correct address.
Referring to Figure 6a, at initial power-up and when not
balancing, the WDT pin is high impedance and will be
pulled high (internally clamped to ~5.6V) if an external
pull-up resistor is present. While balancing and during
normal communication activity, the WDT pin is pulled
low by a precision current source equal to 1.2V/R
TONS
.
(Note: if the secondary volt-second clamp is defeated
by connecting R
TONS
to V
REG
, the watchdog function is
also defeated.) If no valid command byte is written for
1.5 seconds (typical), the WDT output will go back high.
When WDT is high, all balancers will be shut down but
the previously executing balance command still remains
in memory. From this timed-out state, a subsequent valid
command byte will reset the timer, but the
balancers will
only restart if an execute command is written. To defeat
the watchdog function, simply connect the WDT pin to V
–
.
Pause/Resume Balancing (via WDT Pin)
The WDT output pin doubles as a logic input (TTL levels)
which can be driven by an external logic gate as shown in
Figure 6b (no watchdog), or by a PMOS/three-state logic
gate as shown in Figure 6c (with watchdog) to pause and
resume balancing in progress. The external pull-up must
have sufficient drive capability to override the current source
to ground at the WDT pin (= 1.2V/R
TONS
). Provided that
the internal watchdog timer has not independently timed
out, externally pulling the WDT pin high will immediately
pause balancing, and it will resume where it left off when
the pin is released.
OPERATION
