LTC3300IUK-2#TRPBF Datasheet LTC3300IUK-2#PBF, LTC3300HUK-2#PBF, LTC3300ILXE-2#PBF | P34-P36

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

APPLICATIONS INFORMATION

How to Calculate the CRC

One simple method of computing an n-bit CRC is to perform

arithmetic modulo-2 division of the n+1 bit characteristic

polynomial into the m bit message appended with n ze

ros (m+n bits).

Arithmetic modulo-2 division resembles

normal long division absent borrows and carries. At each

intermediate step of the long division, if the leading bit

of the dividend is a 1, a 1 is entered in the quotient and

the dividend is exclusive-ORed bitwise with the divisor.

If the leading bit of the dividend is a 0, a 0 is entered in

the quotient and the dividend is exclusive-ORed bitwise

with n zeros. This process is repeated m times. At the end

of the long division, the quotient is disregarded and the

n-bit remainder is the CRC. This will be more clear in the

example to follow.

For the CRC implementation in the LTC3300-2, n = 4 and

m = 12. The characteristic polynomial employed is x

+ x

+ 1, which is shorthand for 1x

+ 0x

+ 1x

resulting in 10011 for the divisor. The message is the first

12 bits of the balance command. Suppose for example the

desired balance command calls for simultaneous charging

Cell 1 and synchronous discharging of Cell4. The 12-bit

message (MSB first) will be 110000010000. Appending

4 zeros results in 1100000100000000 for the dividend.

The long division is shown in Figure 13a with a resultant

CRC of 1101. Note that the CRC bits in the write balance

command are inverted. Thus the correct 16-bit balance

command is 1100000100000010. Figure13b shows the

same long division procedure being used to check the

CRC of data (command or status) read back from the

LTC3300-2. In this scenario, the remainder after the long

division must be zero (0000) for the data to be valid. Note

that the readback CRC bits must be inverted in the dividend

before performing the division.

An alternate method to calculate the CRC is shown in

Figure 14 in which the balance command bits are input to

a combinational logic circuit comprised solely of 2-input

exclusive-OR gates. This “brute force” implementation is

easily replicated in a few lines of C code.

Figure 13. (a) Long Division Example to Calculate CRC for Writes.

(b) Long Division Example to Check CRC for Reads

1 1 0 1 0 1 1 0 1 0 1 1

1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0

1 0 0 1 1

1 0 1 1 0

1 0 0 1 1

0 1 0 1 0

0 0 0 0 0

1 0 1 0 1

1 0 0 1 1

0 1 1 0 0

0 0 0 0 0

1 1 0 0 0

1 0 0 1 1

1 0 1 1 0

1 0 0 1 1

0 1 0 1 0

0 0 0 0 0

1 0 1 0 0

1 0 0 1 1

0 1 1 1 0

0 0 0 0 0

1 1 1 0 0

1 0 0 1 1

1 1 1 1 0

1 0 0 1 1

REMAINDER = 1 1 0 1 = 4-BIT CRC

1 1 0 1 0 1 1 0 1 0 1 1

1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 1

1 0 0 1 1

1 0 1 1 0

1 0 0 1 1

0 1 0 1 0

0 0 0 0 0

1 0 1 0 1

1 0 0 1 1

0 1 1 0 0

0 0 0 0 0

1 1 0 0 0

1 0 0 1 1

1 0 1 1 0

1 0 0 1 1

0 1 0 1 0

0 0 0 0 0

1 0 1 0 1

1 0 0 1 1

0 1 1 0 1

0 0 0 0 0

1 1 0 1 0

1 0 0 1 1

REMAINDER = 0

33002 F13

0 0 1 0 = 4-BIT CRC INVERTED

READBACK = 1100000100000010

DIVIDEND = 1100000100001101

(b)(a)

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

APPLICATIONS INFORMATION

Serial Communication Using the LTC6803 and LTC6804

The LTC3300-2 is compatible with and convenient to

use with all LTC monitor chips, such as the LTC6803 and

LTC6804. Figure 17 in the Typical Applications section

shows the serial communications connections for a joint

LTC3300-2/LTC6803-2 BMS using a common micropro

cessor SPI

port. The SCKI, SDI, and SDO lines of the low-

ermost

LTC3300-2 and LTC6803-2 are tied together. The

CSBI

lines, however, must be separated to prevent talking

to both ICs at the same time. This is easily accomplished

by using one of the GPIO outputs from the LTC6803-2

to gate and invert the CSBI line to the LTC3300-2. In this

setup, communicating to the LTC6803-2 is no different

than without the LTC3300-2, as the GPIO1 output bit is

normally high. To talk to the LTC3300-2, written commands

must be “bookended” with a GPIO1 negation write to the

LTC6803-2 prior to talking to the LTC3300-2 and with

a GPIO1 assertion write after talking to the LTC3300-2.

Communication to all non-ground referred LTC3300-2 and

LTC6803-2 ICs is done through digital isolators.

The Typical Application shown on the back page of this

data

sheet shows the serial communication connections

for a joint LTC3300-2/LTC6804-2 BMS. Each stacked

12-cell module contains two LTC3300-2 ICs and a single

LTC6804-2 monitor IC. . The LTC6804-2 in the module

is configured to provide an effective SPI port output at its

GPIO3, GPIO4, and GPIO5 pins which connect directly to

the low side communication pins (CSBI, SDI=SDO, SCKI)

of the lower LTC3300-2. The upper LTC3300-2 in each

module receives its serial communication via a digital

isolator from the lower LTC3300-2. Communication to

the lowermost LTC6804-2 and between monitor chips is

done via the LTC6820 and the isoSPI™ interface. In this

application, unused battery cells can be shorted from

the bottom of any module (i.e., outside the module, not

on the module board) as shown without any decrease in

monitor accuracy.

Figure 14. Combinational Logic Circuit Implementation of the CRC Calculator

CRC [3]

CRC [2]

CRC [1]

CRC [0]

33002 F14

D6B

“Ø”

D5B

D3B

D1B

D2A

D5A

D3A

D1A

D4B

D2B

D4A

D6A

CRC [2]

CRC [1]

CRC [0]

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

PCB Layout Considerations

The LTC3300-2 is capable of operation with as much as

40V between BOOST

and V

–

. Care should be taken on

the PCB layout to maintain physical separation of traces

at different potentials. The pinout of the LTC3300-2 was

chosen to facilitate this physical separation. There is no

more than 8.4V between any two adjacent pins with the

exception of one instance (BOOST to BOOST

–

). In this

instance, the BOOST pin is pin-strapped in the applica-

tion to

–

or V

REG

and does not need to route far from

the LTC3300-2. The package body is used to separate

the highest voltage (e.g., 25.2V) from the lowest voltage

(0V). As an example, Figure15 shows the DC voltage on

each pin with respect to V

–

when six 4.2V battery cells

are connected to the LTC3300-2.

Additional “good practice” layout considerations are as

follows:

1. The V

REG

pin should be bypassed to the exposed pad

and to V

–

, each with 1µF or larger capacitors as close

to the LTC3300-2 as possible.

APPLICATIONS INFORMATION

2. The differential cell inputs (C6 to C5, C5 to C4, …, C1 to

exposed pad) should be bypassed with a 1µF or larger

capacitor

as close to the LTC3300-2 as possible. This

is in addition to bulk capacitance present in the power

stages.

3. Pin 21 (V

–

) is the ground sense for current sense resis-

tors connected

to I1S-I6S and I1P (seven resistors).

Pin 21 should be Kelvined as well as possible with low

impedance traces to the ground side of these resistors

before connecting to the LTC3300-2 exposed pad.

4. Cell inputs C1 to C5 are the ground sense for current

sense resistors connected to I2P-I6P (five resistors).

These pins should be Kelvined as well as possible

with low impedance traces to the ground side of these

resistors.

5. The ground side of the maximum on-time setting resis

tors connected

to the RTONS and RTONP pins should

be Kelvined to Pin 21 (V

–

) before connecting to the

LTC3300-2 exposed pad.

6. Trace lengths from the LTC3300-2 gate drive outputs

(G1S-G6S and G1P-G6P) and current sense inputs

(I1S-I6S and I1P-I6P) should be as short as possible.

7. The boosted gate drive components (diode and ca

pacitor), if used, should form a tight loop close to the

LTC3300-2 C6, BOOST

, and BOOST

–

pins.

8. For the external power components (transformer, FETs

and current sense resistors), it is important to keep the

area encircled by the two high speed current switching

loops (primary and secondary) as tight as possible.

This is greatly aided by having two additional bypass

capacitors local to the power circuit: one differential

cell to cell and one from the transformer secondary to

local V

–

A representative layout incorporating all of these recom-

mendations is

implemented on the DC2064A demo board

for the LTC3300-1 companion product (with further ex-

planation in

its accompanying demo board manual). To

accommodate

the LTC3300-2, only minor modifications

to Pins 43 to 47 connections need to be made. PCB layout

files (.GRB) are also available from the factory.

Figure 15. Typical Pin Voltages for Six 4.2V Cells

LTC3300-2

(EXPOSED PAD = 0V)

0V TO 4.8V

21V

16.8V TO 25.2V

16.8V

12.6V TO 21V

12.6V

8.4V TO 16.8V

8.4V

4.2V TO 12.6V

4.2V

G6S—PIN 1

I6S

G5S

I5S

G4S

I4S

G3S

I3S

G2S

I2S

G1S

I1S

G5P

I5P

G4P

I4P

G3P

I3P

G2P

I2P

REG

BOOST

–

BOOST

G6P

I6P

1.2V

0V/4.8V

0V TO 4.8V

0V TO 8.4V

4.2V

RTONS

RTONP

CTRL

CSBI

SCKI

SDI

SDO

WDT

–

I1P

G1P

4.8V

0V/4.8V

21V TO 25.2V

25.2V TO 29.4V

25.2V

21V TO 29.4V

21V

33002 F15

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