LTC3300-2
22
33002f
For more information www.linear.com/LTC3300-2
OPERATION
ACTIVE
5.6V
LTC3300-2
V
REG
WDT
RTONS
R
TONS
33002 F06a
V
1.2V
R
TONS
R
WDT
ACTIVE
5.6V
LTC3300-2V
TH
= 1.4V
V
REG
WDT
RTONS
R
TONS
PAUSE/
RESUME
33002 F06b
1.2V
R
TONS
ACTIVE
5.6V
V
REG
V
REG
TO TRANSFORMER
SECONDARY WINDINGS
LTC3300-2
WDT
RTONS
R
TONS
V
REG
V
REG
PAUSE/
RESUME
EITHER/OR
PAUSE/
RESUME
33002 F06c
1.2V
R
TONS
R
SEC_OVP
(6a) Watchdog Timer Only (WDT = V
to Defeat) (6b) Pause/Resume Balancing Only
(6c) Watchdog Timer with Pause/Resume Balancing and Secondary Winding OVP Protection
Figure 6. WDT Pin Connection Options
Secondary Winding OVP Function (via WDT pin)
The precision current source pull-down on the WDT pin
during balancing can be used to construct an accurate
secondary winding OVP protection circuit as shown in
Figure 6c. A second external resistor, scaled to R
TONS
and connected to the transformer secondary winding, is
used to set the comparator threshold. An NMOS cascode
device (with gate tied to V
REG
) is also needed to protect
the WDT pin from high voltage. The secondary winding
OVP thresholds are given by:
V
SEC|OVP(RISING)
= 1.4V + 1.2V • (R
SEC_OVP
/R
TONS
)
V
SEC|OVP(FALLING)
= 1.4V + 1.05V • (R
SEC_OVP
/R
TONS
)
This comparator will protect the LTC3300-2 application
circuit if the secondary winding connection to the battery
stack is lost while balancing and the secondary winding
voltage is still increasing as a result of that balancing. The
balance command remains stored in memory, and active
balancing will resume where it left off if the stack voltage
subsequently falls to a safer level.
Single
Transformer Application (CTRL = V
REG
)
Figure 7 shows a fully populated LTC3300-2 application
employing all six balancers with a single shared custom
transformer. In this application, the transformer has six
primary windings coupled to a single secondary winding.
Only one balancer can be active at a given time as all six
share the secondary gate driver G1S and secondary current
sense input I1S. The unused gate driver outputs G2S-G6S
must be left floating and the unused current sense inputs
I2S-I6S should be connected to V
. Any balance command
which attempts to operate more than one balancer at a time
will be ignored. This application represents the minimum
component count active balancer achievable.
LTC3300-2
23
33002f
For more information www.linear.com/LTC3300-2
OPERATION
Figure 7. LTC3300-2 6-Cell Active Balancer Module Showing Power Connections for the Single Transformer Application (CTRL = V
REG
)
10µH
EACH
1:1
UP TO CELL 12
25mΩ
CELL 6
+
10µH
25mΩ
CELL 5
+
10µH
10µH
10µH
10µH
25mΩ
CELL 4
+
25mΩ
CELL 3
+
25mΩ
CELL 2
+
25mΩ
CELL 1
NC
33002 F07
6.98k
+
25mΩ
22.6k10µF
BOOST
+
C6
G6P
I6P
C5
G5P
I5P
C4
G4P
I4P
C3
G3P
I3P
C2
G2P
LTC3300-2
I2P
C1
G1P
G1S
I1S
G2S-G6S
I2S-I6S
V
CTRL
BOOST
V
REG
10µF
I1P
BOOST
RTONSRTONP
0.1µF
6.8Ω
SERIAL
COMMUNICATION
RELATED
PINS
10µF
10µF
10µF
10µF
10µF
A4
A3
A2
A1
A0
CSBI
SCKI
SDI
SDO
WDT
LTC3300-2
24
33002f
For more information www.linear.com/LTC3300-2
CSBI
SCKI
SDI
MSB (CMD) LSB (CMD)
33002 F08
CSBI
SCKI
SDI
MSB (CMD) LSB (CMD)
LSB (DATA)
MSB (DATA)
(8a) Transmission Format (Write)
(8b) Transmission Format (Read)
LSB (DATA)
MSB (DATA)SDO
Figure 8.
OPERATION
SERIAL PORT OPERATION
Overview
The LTC3300-2 has an SPI bus compatible serial port.
Devices can be connected in parallel, using digital isolators.
Multiple devices are uniquely identified by a part address
determined by the A0 to A4 pins.
Physical Layer
On the LTC3300-2, four pins comprise the serial interface:
CSBI, SCKI, SDI and SDO. The SDO and SDI pins may
be tied together, if desired, to form a single bidirectional
port. Five address pins (A0 to A4) set the part address.
All serial communication related pins are voltage mode
with voltage levels referenced to the V
REG
and V
supplies.
Data Link Layer
Clock Phase and Polarity:
The LTC3300-2 SPI-compatible
interface is configured to operate in a system using
CPHA = 1 and CPOL
= 1.
Consequently, data on SDI must
be stable during the rising edge of SCKI.
Data Transfers:
Every byte consists of 8 bits. Bytes are
transferred with the most significant bit (MSB) first. On a
write, the data value on SDI is latched into the device on
the rising edge of SCKI (Figure 8a). Similarly, on a read,
the data value on SDO is valid during the rising edge of
SCKI and transitions on the falling edge of
SCKI (Figure
8b).
CSBI must remain low for the entire duration of a com-
mand sequence
,
including between a command byte and
subsequent data. On a write command, data is latched in
on the rising edge of CSBI.

LTC3300IUK-2#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Addressable Hi Eff Bi-dir Multicell Bat
Lifecycle:
New from this manufacturer.
Delivery:
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