LTC3300IUK-2#TRPBF Datasheet LTC3300IUK-2#PBF, LTC3300HUK-2#PBF, LTC3300ILXE-2#PBF | P25-P27

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

OPERATION

Command Byte

All communication to the LTC3300-2 takes place with CSBI

logic low. The first 8 clocked in data bits after a high-to-

low transition on CSBI represent the command byte. The

8-bit command byte is written MSB first per Table 2. The

first 5 bits must match the fixed pin-strapped address

[A4 A3 A2 A1 A0] for the individual device, or all sub-

sequent data

will be ignored until CSBI transitions high

and then low again. The 6th and 7th bits program one of

four commands as shown in Table 3. The 8th bit in the

command byte must be set such that the entire 8-bit com

mand byte has even parity. If the parity is incorrect, the

current

balance command being executed (from the last

previously successful write) is terminated immediately and

all subsequent (write) data is ignored until CSBI transi

tions high and then low again. Incorrect parity takes this

action

whether or not the address matches. This thereby

provides a fast means to immediately terminate balancing-

in-progress by intentionally writing a command byte with

incorrect parity.

Table 2. Command Byte Bit Mapping

(Defaults to 0x00 in Reset State)

(MSB)

A2 A1 A0 CMDA CMDB Parity Bit

(LSB)

Table 3. Command Bits

CMDA CMDB COMMUNICATION ACTION

0 0 Write Balance Command (without Executing)

0 1 Readback Balance Command

1 0 Read Balance Status

1 1 Execute Balance Command

Write Balance Command

If the command bits program Write Balance Command,

all subsequent write data must be exactly 16 bits (before

CSBI transitions high) or it will be ignored. The internal

command holding register will be cleared which can be

verified on readback. The current balance command being

executed (from the last previously successful write) will

continue, but all active balancing will be turned off if an

Execute Balance Command is subsequently written. Only

the individual LTC3300-2 in the stack with the matching

address will load in the write data. The 16-bit write balance

command is written MSB first per Table 4.

The first 12 bits of the 16-bit balance command are used

to indicate which balancer (or balancers) is active and in

which direction (charge or discharge). Each of the 6 cell

balancers is controlled by 2 bits of this data per Table 5.

The balancing algorithm for a given cell is:

Charge Cell n: Ramp up to I

PEAK

in secondary winding,

ramp down to I

ZERO

in primary winding. Repeat.

Discharge Cell n (Synchronous): Ramp up to Ipeak in

primary winding, ramp down

to I

ZERO

in secondary

winding. Repeat.

Table 5. Cell Balancer Control Bits

Dn A Dn B BALANCING ACTION (n = 1 to 6)

0 0 None

0 1 Discharge Cell n (Nonsynchronous)

1 0 Discharge Cell n (Synchronous)

1 1 Charge Cell n

Table 4. Write Balance Command Data Bit Mapping (Defaults to 0x000F in Reset State)

D1A

(MSB)

D1B D2A D2B D3A D3B D4A D4B D5A D5B D6A D6B CRC[3] CRC[2] CRC[1] CRC[0]

(LSB)

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

OPERATION

For nonsynchronous discharging of cell n, both the sec-

ondary winding

gate drive and (zero) current sense amp

are disabled. The secondary current will conduct either

through the body diode of the secondary switch (if pres

ent) or through a substitute Schottky diode. The primary

will only turn on again after the secondary winding Volt-

sec clamp times out. In a bidirectional application with a

secondary switch, it may be possible to achieve slightly

higher discharge efficiency by opting for nonsynchronous

discharge mode (if the gate charge savings exceed the

added diode drop losses) but the balancing current will be

less predictable because the secondary winding Volt-sec

clamp must be set longer than the expected time for the

current to hit zero in order to guarantee no current rever

sal. In the case where a Schottky diode replaces the sec-

ondar

y switch,

it is possible to build a undirectional

discharge-only balancing application charging an isolated

auxiliary cell as shown in Figure 16 in the Typical Applica

tions section.

In the CTRL = 1 application of Figure 7 employing a single

transformer which can only balance one cell at a time,

any command requesting simultaneous balancing of more

than one cell will be ignored. All active balancing will be

turned

off if an Execute Balance Command is subse-

quently written.

The last 4 bits of the 16-bit balance command are used

for packet error checking (PEC). The 16 bits of write data

(12-bit message plus 4-bit CRC) are input to a cyclic re

dundancy check (CRC) block employing the International

Telecommunication Union CRC-4 standard characteristic

polynomial:

+ x + 1

In the write data, the 4-bit CRC appended to the message

must be selected such that the remainder of the CRC divi

sion is zero. Note that the CRC bits in the Write Balance

Command are inverted. This was done so that an “all zeros”

command is invalid. The LTC3300-2 will ignore the write

data if the remainder is not zero and the internal command

holding register will be cleared which can be verified on

readback. The current balance command being executed

(from the last previously successful write) will continue,

but all active balancing will be turned off if an Execute Bal

ance Command is subsequently written. For information

on how to calculate the CRC including an example, refer

to the Applications Information section.

Readback Balance Command

The bit mapping for Readback Balance Command

is identi-

cal

to that for Write Balance Command. If the command

bits

program Readback Balance Command, the 16 bits of

previously written data (latched in 12-bit message plus

newly calculated 4-bit CRC) are shifted out in the same

order bitwise (MSB first) per Table 4. Only the individ-

ual LTC3300-2 in the stack with the matching address

will send out the read data. This command allows for

microprocessor verification of written commands before

executing. Note that the CRC bits in the Readback Balance

Command are also inverted. This was done so that an “all

zeros” readback is invalid.

Read Balance Status

If the command bits program Read Balance Status, 16 bits

of status data (12 bits of data plus associated 4-bit CRC)

are shifted out MSB first per Table 6. Similar to a Readback

Balance Command, the last 4 bits in each 16-bit balance

status are used for error detection. The first 12 bits of

the status are input to a cyclic redundancy check (CRC)

block employing the same characteristic polynomial used

for write commands. The LTC3300-2 will calculate and

append the appropriate 4-bit CRC to the outgoing 12-bit

message which can then be used for microprocessor er

Table 6. Read Balance Status Data Bit Mapping (defaults to 0x000F in Reset State)

Gate

Drive 1

(MSB)

Gate

Drive 2

Gate

Drive 3

Gate

Drive 4

Gate

Drive 5

Gate

Drive 6

Cells

Not OV

Sec

Not OV

Temp

0 0 CRC[3] CRC[2] CRC[1] CRC[0]

(LSB)

LTC3300-2

33002f

For more information www.linear.com/LTC3300-2

OPERATION

ror checking. Only the individual LTC3300-2 in the stack

with the matching address will send out the status data.

Note that

the CRC bits in the Read Balance Status are

inverted.

This was done so that an “all zeros” readback

is invalid.

The first 6 bits of the read balance status indicate if there

is sufficient gate drive for each of the 6 balancers. These

bits correspond to the right-most column in Table 1, but

can only be logic high for a given balancer following an

execute command involving that same balancer. If a bal

ancer is

not active, its Gate Drive OK bit will be logic low.

The

7th, 8th, and 9th bits in the read balance status indicate

that all 6 cells are not overvoltage, that the transformer

secondary is not overvoltage, and that the LTC3300-2 die

is not overtemperature, respectively. These 3 bits can only

be logic high following an execute command involving at

least one balancer. The 10th, 11th, and 12th bits in the

read balance status are currently not used and will always

be logic zero. As an example, if balancers 1 and 4 are both

active with no voltage or temperature faults, the 12-bit

read balance status should

be 100100111000.

Execute Balance Command

the command bits program Execute Balance Command,

the last successfully written and latched in balance com-

mand will

be executed immediately. All subsequent (write)

data

will be ignored until CSBI transitions high and then

low again.

Pause/Resume Balancing (via SPI Port)

The LTC3300-2 provides a simple means to interrupt bal

ancing in

progress (stack wide) and then restart without

having

to rewrite the previous balance command to all

LTC3300-2 ICs in the stack. To pause balancing, simply

write an 8-bit Execute Balance Command with incorrect

parity. To resume balancing, simply write an Execute Bal

ance Command

with the correct parity to each different

address. This feature is useful if precision cell voltage

measurements want to be performed during balancing

with the stack “quiet.” Immediate pausing of balancing

in progress will occur for any 8-bit Command Byte with

incorrect parity.

The restart time is typically 2ms which is the same as the

delayed start time after a new or different balance command

DLY_START

). It is measured from the 8th rising SCKI edge

until the balancer turns on and is illustrated in G25 in the

Typical Performance Characteristics section.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42

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