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MTFDDAK200MAN-1S1AA

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Table 5: Identify Device (Continued)
See Note 1 for setting definitions
Word Bit(s) Setting Default Value Description
48 – – – Trusted Computing feature set options
15 F 0b Shall be cleared to zero
14 F 1b Shall be set to one
13–1 F 0000000000000b Reserved for the Trusted Computing Group
0 F 0b 1 = Trusted Computing feature set is supported
49 – – – Capabilities
15–14 F 00b Reserved for the IDENTIFY PACKET DEVICE command
13 F 1b 1 = Standby timer values as specified in this standard are
supported
– – – 0 = Standby timer values shall be managed by the device
12 F 0b Reserved for the IDENTIFY PACKET DEVICE command
11 F 1b 1 = IORDY is supported
– – – 0 = IORDY may be supported
10 F 1b 1 = IORDY may be disabled
9 – 1b 1 = LBA is supported
8 F 1b 1 = DMA is supported
7–0 F 00000000b Retired
50 – – – Capabilities
15 F 0b Shall be cleared to zero
14 F 1b Shall be set to one
13–2 F 000000000000b Reserved
1 X 0b Obsolete
0 F 1b Shall be set to one to indicate a vendor-specific standby tim-
er value minimum
51 – ( )X 0000h 0000h Obsolete
53 15–3 F 0000000000000b Reserved
2 F 1b 1 = The fields reported in word 88 are valid
0 = The fields reported in word 88 are not valid
1 F 1b 1 = The fields reported in words (70:64) are valid
0 = the fields reported in words (70:64) are not valid
0 X 1b Obsolete
54 – ( )X 3FFFh 0010h
003Fh FC10h
00FBh
Obsolete
P400m 2.5-Inch NAND Flash SSD
Device ID
PDF: 09005aef84952553
p400m_2_5.pdf - Rev. H 11/13 EN
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Table 5: Identify Device (Continued)
See Note 1 for setting definitions
Word Bit(s) Setting Default Value Description
59 15 F 1b 1 = The BLOCK ERASE EXT command is supported
14 F 1b 1 = The OVERWRITE EXT command is supported
13 F 0b 1 = The CRYPTO SCRAMBLE EXT command is supported
12 F 1b 1 = The sanitize feature set is supported
11–9 F 000b Reserved
8 V 1b 1 = Multiple sector settings are valid
7–0 V 00010000b xxh = Current setting for number of logical sectors that shall
be transferred per DRQ data block on READ/WRITE MULTI-
PLE commands
60 – M(F) Varies by capacity Total number of user addressable logical sectors
62 – ( )X 0000h Obsolete
63 15–11 F 00000b Reserved
10 V 0b 1 = Multiword DMA mode 2 is selected
0 = Multiword DMA mode 2 is not selected
9 V 0b 1 = Multiword DMA mode 1 is selected
0 = Multiword DMA mode 1 is not selected
8 V 0b 1 = Multiword DMA mode 0 is selected
0 = Multiword DMA mode 0 is not selected
7–3 F 0000b Reserved
2 F 1b 1 = Multiword DMA mode 2 and below are supported
1 F 1b 1 = Multiword DMA mode 1 and below are supported
0 F 1b 1 = Multiword DMA mode 0 is supported
64 15–8 F 00h Reserved
7–0 F 03h PIO modes is supported
65 – F 0078h Minimum Multiword DMA transfer cycle time per word
Cycle time in nanoseconds
66 – F 0078h Manufacturer's recommended Multiword DMA transfer cy-
cle time
Cycle time in nanoseconds
67 – F 0078h Minimum PIO transfer cycle time without flow control
Cycle time in nanoseconds
68 – F 0078h Minimum PIO transfer cycle time with IORDY flow control
Cycle time in nanoseconds
P400m 2.5-Inch NAND Flash SSD
Device ID
PDF: 09005aef84952553
p400m_2_5.pdf - Rev. H 11/13 EN
8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Table 5: Identify Device (Continued)
See Note 1 for setting definitions
Word Bit(s) Setting Default Value Description
69 – F – Additional supported
15 F 0b 1 = CFast specification is supported
14 F 1b 1 = Deterministic read after trim is supported
13 F 0b 1 = Long physical sector alignment error reporting control is
supported
12 F 0b 1 = DEVICE CONFIGURATION IDENTIFY DMA and DEVICE
CONFIGURATION SET DMA are supported
11 F 0b 1 = READ BUFFER DMA is supported
10 F 0b 1 = WRITE BUFFER DMA is supported
9 F 0b 1 = SET MAX PASSWORD DMA and SET MAX UNLOCK DMA
are supported
8 F 0b 1 = DOWNLOAD MICROCODE DMA is supported
7 F 0b Reserved for IEEE-1667
6 F 0b 1 = Optional ATA device 28-bit commands are supported
5 F 0b 1 = Read zero after trim is supported
4–0 F 00000b Reserved
70 – F 0000h Reserved
71 – F 0000h 0000h
0000h 0000h
Reserved for the IDENTIFY PACKET DEVICE command
75 – – – Queue depth
15–5 F 00000000000b Reserved
4–0 F 11111b Maximum queue depth - 1
76 – – – Serial ATA capabilities
15–13 F 000b Reserved
12 F 1b Native command queuing priority information is supported
11 F 0b Unload while NCQ commands are outstanding is supported
10 F 1b Physical event counters are supported
9 F 1b Receipt of host-initiated interface power management re-
quests is supported
8 F 1b Native command queuing is supported
7–4 F 0000b Reserved for future Serial ATA signaling speed grades
3 F 1b 1 = Serial ATA Gen-3 speed (6.0 Gb/s) is supported
2 F 1b 1 = Serial ATA Gen-2 speed (3.0 Gb/s) is supported
1 F 1b 1 = Serial ATA Gen-1 speed (1.5 Gb/s) is supported
0 F 0b Reserved (set to 0)
P400m 2.5-Inch NAND Flash SSD
Device ID
PDF: 09005aef84952553
p400m_2_5.pdf - Rev. H 11/13 EN
9
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
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MTFDDAK200MAN-1S1AA

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SSD 200GB 2.5" MLC SATA III 5V
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