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AD5336BRU

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
REV. 0
AD5334/AD5335/AD5336/AD5344
–4–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5334/AD5335/AD5336/AD5344 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . .–0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to GND . . . . . . –0.3 V to V
DD
+ 0.3 V
Reference Input Voltage to GND . . . . –0.3 V to V
DD
+ 0.3 V
V
OUT
to GND . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
TSSOP Package
Power Dissipation . . . . . . . . . . . . . . . (T
J
max – T
A
)/θ
JA
mW
θ
JA
Thermal Impedance (24-Lead TSSOP) . . . . . 128°C/W
θ
JA
Thermal Impedance (28-Lead TSSOP) . . . . . 97.9°C/W
θ
JC
Thermal Impedance (24-Lead TSSOP) . . . . . . 42°C/W
θ
JC
Thermal Impedance (28-Lead TSSOP) . . . . . . 14°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C
Time at Peak Temperature . . . . . . . . . . . . .10 sec to 40 sec
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD5334BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-24
AD5335BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-24
AD5336BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-28
AD5344BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-28
REV. 0
AD5334/AD5335/AD5336/AD5344
–5–
AD5334 FUNCTIONAL BLOCK DIAGRAM
V
OUT
A
BUFFER
GND
AD5334
V
OUT
B
BUFFER
V
OUT
C
BUFFER
V
OUT
D
BUFFER
POWER-ON
RESET
TO ALL DACS
AND BUFFERS
POWER-DOWN
LOGIC
PD
DAC
REGISTER
8-BIT
DAC
8-BIT
DAC
INPUT
REGISTER
V
REF
C/D
INTER-
FACE
LOGIC
V
DD
V
REF
A/B
GAIN
DB
7
DB
0
CS
WR
A0
A1
CLR
LDAC
.
.
.
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
8-BIT
DAC
8-BIT
DAC
8-BIT
DAC
AD5334 PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1V
REF
C/D Unbuffered Reference Input for DACs C and D.
2V
REF
A/B Unbuffered Reference Input for DACs A and B.
3V
OUT
A Output of DAC A. Buffered Output with Rail-to-Rail Operation.
4V
OUT
B Output of DAC B. Buffered Output with Rail-to-Rail Operation.
5V
OUT
C Output of DAC C. Buffered Output with Rail-to-Rail Operation.
6V
OUT
D Output of DAC D. Buffered Output with Rail-to-Rail Operation.
7 GND Ground Reference Point for All Circuitry on the Part.
8 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
9 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
10 A0 LSB Address Pin for Selecting which DAC Is to Be Written to.
11 A1 MSB Address Pin for Selecting which DAC Is to Be Written to.
12 LDAC Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers.
This allows all DAC outputs to be simultaneously updated.
13 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
14 V
DD
Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
15–22 DB
0
–DB
7
Eight Parallel Data Inputs. DB
7
is the MSB of these eight bits.
23 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0–V
REF
or 0–2 V
REF
24 CLR Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros.
AD5334 PIN CONFIGURATION
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD5334
LDAC
A1
A0
WR
CS
V
REF
C/D
V
REF
A/B
V
OUT
A
V
OUT
B
GND
V
OUT
D
V
OUT
C
PD
V
DD
DB
0
DB
1
DB
2
CLR
GAIN
DB
7
DB
6
DB
3
DB
4
DB
5
8-BIT
REV. 0
AD5334/AD5335/AD5336/AD5344
–6–
AD5335 FUNCTIONAL BLOCK DIAGRAM
.
.
.
.
.
.
V
OUT
A
BUFFER
GND
AD5335
V
OUT
B
V
OUT
C
V
OUT
D
TO ALL DACS
AND BUFFERS
POWER-DOWN
LOGIC
PD
DAC
REGISTER
V
REF
C/D
INTER-
FACE
LOGIC
V
DD
V
REF
A/B
HBEN
DB
7
DB
0
CS
WR
A0
A1
CLR
LDAC
RESET
POWER-ON
RESET
HIGH BYTE
REGISTER
BUFFER
BUFFER
BUFFER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
LOW BYTE
REGISTER
HIGH BYTE
REGISTER
HIGH BYTE
REGISTER
HIGH BYTE
REGISTER
LOW BYTE
REGISTER
LOW BYTE
REGISTER
LOW BYTE
REGISTER
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
AD5335 PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1V
REF
C/D Unbuffered Reference Input for DACs C and D.
2V
REF
A/B Unbuffered Reference Input for DACs A and B.
3V
OUT
A Output of DAC A. Buffered output with rail-to-rail operation.
4V
OUT
B Output of DAC B. Buffered output with rail-to-rail operation.
5V
OUT
C Output of DAC C. Buffered output with rail-to-rail operation.
6V
OUT
D Output of DAC D. Buffered output with rail-to-rail operation.
7 GND Ground Reference Point for All Circuitry on the Part.
8 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
9 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
10 A0 LSB Address Pin for Selecting which DAC Is to Be Written to.
11 A1 MSB Address Pin for Selecting which DAC Is to Be Written to.
12 LDAC Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers.
This allows all DAC outputs to be simultaneously updated.
13 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
14 V
DD
Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
15–22 DB
0
–DB
7
Eight Parallel Data Inputs. DB
7
is the MSB of these eight bits.
23 HBEN This pin is used when writing to the device to determine if data is written to the high byte register or the
low byte register.
24 CLR Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros.
AD5335 PIN CONFIGURATION
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD5335
LDAC
A1
A0
WR
CS
V
REF
C/D
V
REF
A/B
V
OUT
A
V
OUT
B
GND
V
OUT
D
V
OUT
C
PD
V
DD
DB
0
DB
1
DB
2
CLR
HBEN
DB
7
DB
6
DB
3
DB
4
DB
5
10-BIT
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

AD5336BRU

Mfr. #:
Buy AD5336BRU
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Quad 10-Bit
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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