ADV212
Rev. B | Page 10 of 44
DREQ/DACK DMA MODE—SINGLE FIFO READ OPERATION
Table 7.
Parameter Mnemonic Min Typ Max Unit
DREQ Pulse Width DREQ
PULSE
1 JCLK
1
15 JCLK
1
ns
DACK Assert to Subsequent DREQ Delay
t
DREQ
2.5 JCLK
1
3.5 × JCLK + 9.0
1
ns
RD to DACK Setup
t
RD
SU
0 ns
DACK to Data Valid
t
RD
2.5 11 ns
Data Hold t
HD
1.5 ns
DACK Assert Pulse Width DACK
LOW
2 JCLK
1
ns
DACK Deassert Pulse Width DACK
HIGH
2 JCLK
1
ns
RD Hold after DACK Deassert
t
RD
HD
0 ns
RD Assert to FSRQ Deassert (FIFO Empty) RDFSRQ
1.5 JCLK
1
2.5 × JCLK + 9.0
1
ns
DACK to DREQ Deassert (DR × PULS = 0)
t
DREQ
RTN
2.5 JCLK
1
3.5 × JCLK + 9.0
1
ns
1
For a definition of JCLK, see Figure 32.
RD
DACK
DREQ
HDATA 0 1 2
t
RD
t
HD
DREQ
PULSE
t
DREQ
t
RD
SU
t
RD
HD
DACK
HIGH
DACK
LOW
06389-018
Figure 9. Single Read for
DREQ
/
DACK
DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1[14:11] Not Programmed to a Value of 0000)
RD
DACK
DREQ
HDATA
0 1 2
t
RD
t
HD
t
DREQ
RTN
t
RD
SU
t
RD
HD
DACK
HIGH
DACK
LOW
06389-019
Figure 10. Single Read for
DREQ
/
DACK
DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000)
