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ADV212BBCZRL-150

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45
ADV212
Rev. B | Page 24 of 44
121-Ball Package 144-Ball Package
Pin No. Location Pin No. Location Mnemonic
Pins
Used Type Description
1, 4, 9,11,
23, 33, 39,
45, 49 to
51, 55, 56,
60 to 62,
66, 67, 71
to 73, 77,
83, 89, 99,
110, 111,
118, 121
A1, A4, A9,
A11, C1,
C11, D6, E1,
E5 to E7,
E11, F1, F5
to F7, F11,
G1, G5 to
G7, G11,
H6, J1, J11,
K11, L1, L8,
L11
1, 5 to 8, 12,
17, 20, 29,
32, 41, 44,
52 to 56, 65
to 68, 77 to
81, 89 to
93, 101,
104, 105,
113, 116,
125, 128,
133, 137 to
140, 143,
144
A1, A5 to
A8, A12, B5,
B8, C5, C8,
D5, D8, E4
to E8, F5 to
F8, G5 to
G9, H5 to
H9, J5, J8,
J9, K5, K8,
L5, L8, M1,
M5 to M8,
M11, M12
DGND 29/45 GND Ground.
17, 28, 30,
38, 52, 74,
82, 93, 104
to 106
B6, C6, C8,
D5, E8, G8,
H5, J5, K5
to K7
16, 21, 28,
33, 40, 45,
112, 117,
124, 129
B4, B9, C4,
C9, D4, D9,
K4, K9, L4,
L9
IOVDD 11/10 V Positive Supply for Input/Output.
1
In fly-by mode DMA, the functions of the
RD
and
WE
signals (for DMA only) are reversed. This allows a host to move data between an external device and the ADV212
with the use of a single strobe.
2
In encode mode with fly-by DMA, the host can use the
RDFB
signal (
WE
pin) to simultaneously read from the ADV212 and write to an external device such as memory.
3
In decode mode with fly-by DMA, the host can use the
WEFB
signal (
RD
pin) to simultaneously read from the external device and write to the ADV212.
ADV212
Rev. B | Page 25 of 44
THEORY OF OPERATION
The input video or pixel data is passed to the ADV212 pixel
interface, and samples are deinterleaved and passed to the
wavelet engine, which decomposes each tile or frame into
subbands using the 5/3 or 9/7 filters. The resultant wavelet
coefficients are then written to the internal memory. The
entropy CODECs code the image data so that it conforms
to the JPEG2000 standard. An internal DMA provides high
bandwidth memory-to-memory transfers, as well as high
performance transfers between functional blocks and memory.
WAVELET ENGINE
The ADV212 provides a dedicated wavelet transform processor
based on the Analog Devices, Inc., proven and patented SURF®
technology. This processor can perform up to six wavelet
decomposition levels on a tile. In encode mode, the wavelet
transform processor takes in uncompressed samples, performs
the wavelet transform and quantization, and writes the wavelet
coefficients in all frequency subbands to the internal memory.
Each of these subbands is further broken down into code
blocks. The code-block dimensions can be user defined and are
used by the wavelet transform processor to organize the wavelet
coefficients into code blocks when writing to the internal
memory. Each completed code block is then entropy coded by
one of the entropy CODECs.
In decode mode, wavelet coefficients are read from internal
memory and recomposed into uncompressed samples.
ENTROPY CODECS
The entropy CODEC block performs context modeling and
arithmetic coding on a code block of the wavelet coefficients.
Additionally, this block also performs the distortion metric
calculations during compression that are required for optimal
rate and distortion performance. Because the entropy coding
process is the most computationally intensive operation in the
JPEG2000 compression process, three dedicated hardware
entropy CODECs are provided on the ADV212.
EMBEDDED PROCESSOR SYSTEM
The ADV212 incorporates an embedded 32-bit RISC processor.
This processor is used for configuration, control, and manage-
ment of the dedicated hardware functions, as well as for parsing
and generating the JPEG2000 code stream. The processor
system includes memory for both the program and data
memory, the interrupt controller, the standard bus interfaces,
and other hardware functions such as timers and counters.
MEMORY SYSTEM
The main function of the memory system is to manage wavelet
coefficient data, interim code-block attribute data, and
temporary workspace for creating, parsing, and storing the
JPEG2000 code stream. The memory system can also be used
for the program and data memory for the embedded processor.
INTERNAL DMA ENGINE
The internal DMA engine provides high bandwidth memory-
to-memory transfers, as well as high performance transfers
between memory and functional blocks. This function is critical
for high speed generation and parsing of the code stream.
ADV212
Rev. B | Page 26 of 44
ADV212 INTERFACES
There are several possible ways to interface to the ADV212
using the VDATA bus and the HDATA bus or the HDATA bus
alone.
VIDEO INTERFACE (VDATA BUS)
The video interface can be used in applications in which
uncompressed pixel data is on a separate bus from compressed
data. For example, it is possible to use the VDATA bus to input
uncompressed video while using the HDATA bus to output the
compressed data. This interface is ideal for applications
requiring very high throughput, such as live video capture.
Optionally, the ADV212 interlaces ITU-R BT.656 resolution
video on the fly prior to wavelet processing, which yields
significantly better compression performance for temporally
coherent frame-based video sources. Additionally, high
definition digital video such as SMPTE 274M (1080i) is
supported using two or more ADV212 devices.
The video interface can support video data or still image data
input/output in 8-/10-/12-bit formats, in YCbCr format, or in
single input mode. YCbCr data must be in 4:2:2 format. When
operating in raw pixel mode, only one component can be
processed by a single ADV212.
Video data can be input/output in several different modes on
the VDATA bus, as described in Table 17. In all these modes,
the pixel clock must be input on the VCLK pin.
Table 17. Video Input/Output Modes
Mode Description
EAV/SAV
Accepts video with embedded EAV/SAV codes, where
the YCbCr data is interleaved onto a single bus.
HVF
Accepts video data accompanied by separate H, V,
and F signals, where YCbCr data is interleaved onto
a single bus.
Raw
Video
Used for still picture data and nonstandard video.
VFRM, VSTRB, and VRDY are used to program the
dimensions of the image. When operating in raw
pixel mode, only one component can be processed
by a single ADV212.
HOST INTERFACE (HDATA BUS)
The ADV212 can connect directly to a wide variety of host
processors and ASICs using an asynchronous SRAM-style
interface, DMA accesses, or streaming mode (JDATA) interface.
The ADV212 supports 16- and 32-bit buses for control and
8-/16-/32-bit buses for data transfer.
The control and data channel bus widths can be specified
independently, which allows the ADV212 to support applica-
tions that require control and data buses of different widths.
The host interface is used for configuration, control, and status
functions, as well as for transferring compressed data streams.
It can be used for uncompressed data transfers in certain
modes. The host interface can be shared by as many as three
concurrent data streams in addition to control and status
communications. The data streams are
• Uncompressed tile data (for example, still image data)
• Fully encoded JPEG2000 code stream (or unpackaged code
blocks)
• Code-block attributes
The ADV212 uses big endian byte alignment for 16- and 32-bit
transfers. All data is left-justified (MSB).
Pixel Input on the Host Interface
Pixel input on the host interface supports 8-/10-/12-/14-/16-bit
raw pixel data formats. It can be used for pixel (still image)
input/output or compressed video output. Because there are no
timing codes or sync signals associated with the input data on
the host interface, dimension registers and internal counters are
used and must be programmed to indicate the start and end of
the frame.
Host Bus Configuration
For maximum flexibility, the host interface provides several
configurations to meet particular system requirements. The
default bus mode uses the same pins to transfer control, status,
and data to and from the ADV212. In this mode, the ADV212
can support 16- and 32-bit control transfers and 8-/16-/32-bit
data transfers. The size of these buses can be selected independ-
ently, allowing, for example, a 16-bit microcontroller to
configure and control the ADV212 while still providing 32-bit
data transfers to an ASIC or external memory system.
DIRECT AND INDIRECT REGISTERS
To minimize pin count and cost, the number of address pins
is limited to four, which yields a total direct address space of
16 locations. These locations are most commonly used by the
external controller and are, therefore, accessible directly. All
other registers in the ADV212 can be accessed indirectly
through the IADDR and IDATA registers.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45

ADV212BBCZRL-150

Mfr. #:
Buy ADV212BBCZRL-150
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs \JPEG 2000 CODEC w/Integrated Controller
Lifecycle:
New from this manufacturer.
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