ADV212
Rev. B | Page 7 of 44
NORMAL HOST MODE—READ OPERATION
Table 5.
Parameter Mnemonic Min Typ Max Unit
RD to ACK, Direct Registers and FIFO Accesses
t
ACK
(direct)
1
5 1.5 × JCLK + 7.0
2
ns
RD to ACK, Indirect Registers
t
ACK
(indirect)
1
10.5 JCLK
2
15.5 × JCLK + 7.0
2
ns
Read Access Time, Direct Registers t
DRD
(direct) 5 1.5 × JCLK + 7.0
2
ns
Read Access Time, Indirect Registers t
DRD
(indirect) 10.5 JCLK
2
15.5 × JCLK + 7.0
2
ns
Data Hold t
HZRD
2 8.5 ns
CS to RD Setup
t
SC
0 ns
Address Setup t
SA
2 ns
CS Hold
t
HC
0 ns
Address Hold t
HA
2 ns
Read Inactive Pulse Width t
RH
2.5 JCLK
2
ns
Read Active Pulse Width t
RL
2.5 JCLK
2
ns
Read Cycle Time, Direct Registers t
RCYC
5.0 JCLK
2
ns
1
Timing relationship between
ACK
falling transition and HDATA valid is not guaranteed. HDATA valid hold time is guaranteed with respect to
RD
rising transition.
A minimum of three JCLK cycles is recommended between
ACK
assert and
RD
deassert.
2
For a definition of JCLK, see Figure 32.
ADDR
t
SA
t
SC
t
HA
t
HC
t
RL
t
ACK
t
DRD
t
HZRD
t
RH
t
RCYC
HDATA
CS
RD
ACK
VALID
06389-011
Figure 4. Normal Host Mode—Read Operation
