ADV212
Rev. B | Page 27 of 44
CONTROL ACCESS REGISTERS
With the exception of the indirect address and data registers
(IADDR and IDATA), all control/status registers in the
ADV212 are 16 bits wide and are half-word (16-bit) addressable
only. When 32-bit host mode is enabled, the upper 16 bits of the
HDATA bus are ignored on writes and return all zeros on reads
of 16-bit registers.
PIN CONFIGURATION AND BUS SIZES/MODES
The ADV212 provides a wide variety of control and data
configurations, which allows it to be used in many applications
with little or no glue logic. The modes described in this section
are configured using the BUSMODE register. In this section,
host refers to normal addressed accesses (
CS
/
RD
/
WE
/ADDR)
and data refers to external DMA accesses (
DREQ
/
DACK
).
32-Bit Host/32-Bit Data
In this mode, the HDATA[31:0] pins provide full 32-bit wide
data access to the pixel channel, code channel, and ATTR
channel FIFOs.
16-Bit Host/32-Bit Data
This mode allows a 16-bit host to configure and communicate
with the ADV212 while allowing 32-bit accesses to the pixel,
xode, and ATTR FIFOs using the external DMA capability.
All addressed host accesses are 16 bits and, therefore, use only
the HDATA[15:0] pins. The HDATA[31:16] pins provide the
additional 16 bits necessary to support the 32-bit external DMA
transfers to and from the FIFOs only.
16-Bit Host/16-Bit Data
This mode uses 16-bit transfers if used for host or external
DMA data transfers.
16-Bit Host/8-Bit Data (JDATA Bus Mode)
This mode provides separate data input/output and host
control interface pins. Host control accesses are 16 bits and use
HDATA[15:0], whereas the dedicated data bus uses JDATA[7:0].
JDATA uses a valid/hold synchronous transfer protocol. The
direction of the JDATA bus is determined by the mode of the
ADV212. If the ADV212 is encoding (compression), JDATA[7:0]
is an output. If the ADV212 is decoding (decompression),
JDATA[7:0] is an input. Host control accesses remain asynchro-
nous. See also the JDATA Mode section.
STAGE REGISTER
Because the ADV212 contains both 16-bit and 32-bit registers
and its internal memory is mapped as 32-bit data, a mechanism
has been provided to allow 16-bit hosts to access these registers
and memory locations using the stage register, which is accessed
as a 16-bit register using HDATA[15:0]. Before writing to the
desired register, the stage register must be written with the
upper (most significant) half-word.
When the host subsequently writes the lower half-word to the
desired control register, HDATA is combined with the prev-
iously staged value to create the required 32-bit value that is
written. When a register is read, the upper (most significant)
half-word is returned immediately on HDATA, and the lower
half-word can be retrieved by reading the stage register on a
subsequent access.
Note that the stage register does not apply to the three data
channels (pixel, code, and ATTR). These channels are always
accessed at the specified data width and do not require the use
of the stage register.
JDATA MODE
JDATA mode is typically used only when the dedicated video
interface (VDATA) is also enabled. This mode allows code
stream data (compressed data compliant with JPEG2000) to be
input or output on a single dedicated 8-bit bus (JDATA[7:0]).
The bus is always an output during compression operations and
an input during decompression.
A 2-pin handshake is used to transfer data over this synchron-
ous interface. VALID is used to indicate that the ADV212 is
ready to provide or accept data and is always an output. HOLD
is always an input and is asserted by the host if it cannot accept/
provide data. For example, JDATA mode allows real-time appli-
cations, in which pixel data is input over the VDATA bus while
the compressed data stream is output over the JDATA bus.
EXTERNAL DMA ENGINE
The external DMA interface is provided to enable high
bandwidth data input/output between an external DMA
controller and the ADV212 data FIFOs. Two independent DMA
channels can each be assigned to any one of the three data
stream FIFOs (pixel, code, and ATTR).
The controller supports asynchronous DMA using a data-
request/data-acknowledge (
DREQ
/
DACK
) protocol in either
single or burst access mode. Additional functionality is
provided for single address compatibility (fly-by) mode and
dedicated chip select (DCS) mode.
