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ADV212BBCZRL-150

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ADV212
Rev. B | Page 30 of 44
PLL REGISTERS
The ADV212 uses the PLL_HI and PLL_LO direct registers to
configure the PLL. Any time the PLL_LO register is modified,
the host must wait at least 20 µs before reading from or writing
to another register. If this delay is not implemented, erratic
behavior may result.
MCLK is the input clock to the ADV212 PLL and is used to
generate the internal JCLK (JPEG2000 processor clock) and
HCLK (embedded CPU clock).
The PLL can be programmed to have any possible final
multiplier value as long as
• JCLK > 50 MHz and < 150 MHz (144-pin version).
• JCLK > 50 MHz and < 115 MHz (121-pin version).
• HCLK < 81 MHz (121-pin version) or HCLK < 108 MHz
(144-pin version).
• JCLK ≥ 2 × VCLK for single-component input.
• JCLK ≥ 2 × VCLK for YCbCr [4:2:2] input.
• In JDATA mode (JDATA), JCLK must be 4 × MCLK
or higher.
• The maximum burst frequency for external DMA modes is
≤ 0.36 JCLK.
• For MCLK frequencies greater than 50 MHz, the input
clock divider must be enabled; that is, IPD must be set
to 1. IPD cannot be enabled for MCLK frequencies
below 20 MHz.
• Deinterlace modes require JCLK ≥ 4 × MCLK.
• It is not recommended to use an LLC output from a video
decoder as a clock source for MCLK.
To achieve the lowest power consumption, an MCLK frequency
of 27 MHz is recommended for a standard definition CCIR 656
input. The PLL circuit is recommended to have a multiplier of
3. This sets JCLK and HCLK to 81 MHz.
LPF
PHASE
DETECT
VCO
JCLK
HCLK
÷2
HCLKD
÷PLLMULT
÷2
LFB
÷2
÷2
÷2
IPD
BYPASS
MCLK
06389-009
Figure 32. PLL Architecture and Control Functions
Table 20. Recommended PLL Register Settings
IPD LFB PLLMULT HCLKD HCLK JCLK
0 0 N 0 N × MCLK N × MCLK
0 0 N 1 N × MCLK/2 N × MCLK
0 1 N 0 2 × N × MCLK 2 × N × MCLK
0 1 N 1 N × MCLK 2 × N × MCLK
1 0 N 0 N × MCLK/2 N × MCLK/2
1 0 N 1 N × MCLK/4 N × MCLK/2
1 1 N 0 N × MCLK N × MCLK
1 1 N 1 N × MCLK/2 N × MCLK
Table 21. Recommended Values for PLL_HI and PLL_LO Registers
Video Standard CLKIN Frequency on MCLK PLL_HI PLL_LO
SMPTE 125M or ITU-R BT.656 (NTSC or PAL) 27 MHz 0x0008 0x0004
SMPTE 293M (525p) 27 MHz 0x0008 0x0004
ITU-R BT.1358 (625p) 27 MHz 0x0008 0x0004
SMPTE 274M (1080i) 74.25 MHz 0x0008 0x0084
ADV212
Rev. B | Page 31 of 44
HARDWARE BOOT MODES AND POWER
CONSIDERATIONS
The boot mode can be configured via hardware using the CFG
pins or via software. The first boot mode after power-up is set
by the CFG pins and should always be as described in the pin
listing. CFG1 is tied to IOVDD through a 10 k resistor and
CFG2 is tied to GND through a 10 k resistor.
There is no special power sequencing requirement for VDD and
IOVDD.
It is strongly recommended that the user place a small decoup-
ling cap close to every power pin and at least one bulk cap on
each supply.
ADV212
Rev. B | Page 32 of 44
VIDEO INPUT FORMATS
The ADV212 supports a wide variety of formats for uncom-
pressed video and still image data. The actual interface and bus
modes selected for transferring uncompressed data dictates the
allowed size of the input data and the number of samples
transferred with each access.
The host interface can support 8-/10-/12-/14-/16-bit data
formats. The video interface can support video data or still
image data input/output. Supported formats are 8-/10-/12-bit
YCbCr formats or single component format. All formats can
support less precision than provided by specifying the actual
data width/precision in the PMODE register.
The maximum allowable data input rate is limited by using
irreversible or reversible compression modes and the data width
(or precision) of the input samples. See Tabl e 22 and Table 24 to
determine the maximum data input rate.
Table 22. Maximum Pixel Data Input Rates (144-Ball Package)
Interface Compression Mode Input Format
Input Rate Limit
Active Resolution
(MSPS)
1
Approximate Minimum
Output Rate, Compressed
Data
2
(Mbps)
Approximate Maximum
Output Rate, Compressed
Data
3
(Mbps)
HDATA Irreversible 8-bit data 45 130 200
Irreversible 10-bit data 45 130 200
Irreversible 12-bit data 45 130 200
Irreversible 16-bit data 45 130 200
Reversible 8-bit data 40 130 200
Reversible 10-bit data 32 130 200
Reversible 12-bit data 27 130 200
Reversible 14-bit data 23 130 200
VDATA Irreversible 8-bit data 65 130 200
Irreversible 10-bit data 65 130 200
Irreversible 12-bit data 65 130 200
Reversible 8-bit data 40 130 200
Reversible 10-bit data 32 130 200
Reversible 12-bit data 27 130 200
1
Input rate limits for HDATA may be less for certain applications depending on input picture size and content, host interface settings, and DMA transfer settings.
2
Minimum guaranteed sustained output rate or minimum sustainable compression rate (input rate/minimum peak output rate).
3
Maximum peak output rate; an output rate above this value is not possible.
Table 23. Maximum Pixel Data Input Rates (121-Ball Package)
Interface Compression Mode Input Format
Input Rate Limit
Active Resolution
(MSPS)
1
Approx Min Output Rate,
Compressed Data
2
(Mbps)
Approx Max Output Rate,
Compressed Data
3
(Mbps)
HDATA Irreversible 8-bit data 34 98 150
Irreversible 10-bit data 34 98 150
Irreversible 12-bit data 34 98 150
Irreversible 16-bit data 34 98 150
Reversible 8-bit data 30 98 150
Reversible 10-bit data 24 98 150
Reversible 12-bit data 20 98 150
Reversible 14-bit data 17 98 150
VDATA Irreversible 8-bit data 48 98 150
Irreversible 10-bit data 48 98 150
Irreversible 12-bit data 48 98 150
Reversible 8-bit data 30 98 150
Reversible 10-bit data 24 98 150
Reversible 12-bit data 20 98 150
1
Input rate limits for HDATA may be less for certain applications depending on input picture size and content, host interface settings, and DMA transfer settings.
2
Minimum guaranteed sustained output rate or minimum sustainable compression rate (input rate/minimum peak output rate).
3
Maximum peak output rate; an output rate above this value is not possible.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45

ADV212BBCZRL-150

Mfr. #:
Buy ADV212BBCZRL-150
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs \JPEG 2000 CODEC w/Integrated Controller
Lifecycle:
New from this manufacturer.
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