ADV212
Rev. B | Page 15 of 44
VDATA MODE TIMING
Table 11.
Parameter Mnemonic Min Typ Max Unit
VCLK to VDATA Valid Delay (VDATA Output) VDATA
TD
12 ns
VDATA Setup to Rising VCLK (VDATA Input) VDATA
SU
4 ns
VDATA Hold from Rising VCLK (VDATA Input) VDATA
HD
4 ns
HSYNC Setup to Rising VCLK HSYNC
SU
3 ns
HSYNC Hold from Rising VCLK HSYNC
HD
4 ns
VCLK to HSYNC Valid Delay HSYNC
TD
12 ns
VSYNC Setup to Rising VCLK VSYNC
SU
3 ns
VSYNC Hold from Rising VCLK VSYNC
HD
4 ns
VCLK to VSYNC Valid Delay VSYNC
TD
12 ns
FIELD Setup to Rising VCLK FIELD
SU
4 ns
FIELD Hold from Rising VCLK FIELD
HD
3 ns
VCLK to FIELD Valid FIELD
TD
12
Decode Slave Data Sync Delay
(HSYNC Low to First 0xFF of EAV/SAV Code)
SYNC DELAY 8
1
VCLK cycles
Decode Slave Data Sync Delay
(HSYNC Low to First Data for HVF Mode)
10
1
VCLK cycles
1
The sync delay value varies according to the application.
Cr Y
Cb Y FF EAV
FF SAV Cb Y
Cr
VCLK
VDATA (IN)
00 00 00 00
VDATA
SU
VDATA
HD
06389-091
Figure 21. Encode Video Mode TimingCCIR 656 Mode
HSYNC
HSYNC
HD
HSYNC
SU
VCLK
Cb
Y Cb
Y
Cr
Y
VDATA (IN)
Cr Y
06389-092
Figure 22. Encode Video Mode TimingHVF Mode (HSYNC Timing)
(HSYNC Programmed for Negative Polarity)
VSYNC
VSYNC
SU
VCLK
FIELD
FIELD
SU
FIELD
HD
VSYNC
HD
06389-093
Figure 23. Encode Video Mode TimingHVF Mode (VSYNC and FIELD Timing)
(VSYNC and FIELD Programmed for Negative Polarity)
ADV212
Rev. B | Page 16 of 44
FIELD
SU
VCLK
VDATA (OUT)
HSYNC (IN)
00 00
VSYNC (IN)
FIELD (IN)
YCbEAVFF
VDATA
TD
VSYNC
HD
HSYNC
SU
HSYNC
HD
SYNC DELAY
VSYNC
SU
06389-094
Figure 24. Decode Video Mode TimingCCIR 656 Mode, Decode Slave
(HSYNC, VSYNC, and FIELD Programmed to Negative Polarity)
FIELD
SU
VDATA
TD
VSYNC
HD
HSYNC
SU
VSYNC
SU
VCLK
Y Cr YCbYCb
HSYNC (IN)
VSYNC (IN)
VDATA (OUT)
FIELD (IN)
SYNC DELAY
HSYNC
HD
06389-095
Figure 25. Decode Video Mode TimingHVF Mode, Decode Slave
(HSYNC, VSYNC, and FIELD Programmed to Negative Polarity)
VCLK
Cb
Y
CrVDATA (OUT)
FF
00
00
SAV
HSYNC (OUT)
VSYNC (OUT)
FIELD (OUT)
Cb
HSYNC
TD
VDATA
TD
VSYNC
TD
FIELD
TD
06389-096
Figure 26. Decode Video Mode TimingCCIR 656 Mode, Decode Master
(HSYNC, VSYNC, and FIELD Programmed to Negative Polarity)
VCLK
Cb
Y Cr
VDATA (OUT)
Cb Y
HSYNC (OUT)
VSYNC (OUT)
FIELD (OUT)
Cr Y Cb Y
VDATA
TD
VSYNC
TD
FIELD
TD
06389-097
Figure 27. Decode Video Mode TimingHVF Mode, Decode Master
(HSYNC, VSYNC, and FIELD Programmed to Negative Polarity)
ADV212
Rev. B | Page 17 of 44
RAW PIXEL MODE TIMING
Table 12.
Parameter Mnemonic Min Typ Max Unit
VCLK to PIXELDATA Valid Delay (PIXELDATA Output)
1
VDATA
TD
12 ns
PIXELDATA Setup to Rising VCLK (PIXELDATA Input) VDATA
SU
4 ns
PIXELDATA Hold from Rising VCLK (PIXELDATA Input) VDATA
HD
4 ns
VCLK to VRDY Valid Delay VRDY
TD
12 ns
VFRM Setup to Rising VCLK (VFRAME Input) VFRM
SU
3 ns
VFRM Hold from Rising VCLK (VFRAME Input) VFRM
HD
4 ns
VCLK to VFRM Valid Delay (VFRAME Output) VFRM
TD
12 ns
VSTRB Setup to Rising VCLK VSTRB
SU
4 ns
VSTRB Hold from Rising VCLK VSTRB
HD
3 ns
1
PIXELDATA is the actual data on the VDATA bus; pins and bus width depend on it but timing does not.
RAW PIXEL MODE—ENCODE
VCLK
PIXEL 1 PIXEL 2 PIXEL 3
VSTRB
HD
VFRM
SU
VFRM
HD
VRDY
TD
VSTRB
SU
VDATA
HD
VDATA
SU
VFRM (IN)
VSTRB (IN)
VRDY (OUT)
PIXELDATA (IN)
RAW PIXEL MODE—DECODE
VCLK
PIXEL 1 PIXEL 2
PIXEL 3
VSTRB
SU
VSTRB
HD
VFRM
TD
VDATA
TD
VRDY
TD
VFRM (OUT)
VSTRB (IN)
VRDY (OUT)
PIXELDATA (OUT)
06389-031
Figure 28. Raw Pixel Modes

ADV212BBCZRL-150

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs \JPEG 2000 CODEC w/Integrated Controller
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New from this manufacturer.
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